Half Interlock Latch Circuit for High-Density Fuse Banks
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Solution Overview
Problem
The challenge in achieving high-density fuse banks in memory devices is exacerbated by the large area occupied by latch circuitry, which also increases the likelihood of soft errors due to particle strikes, leading to uncorrectable error correction code (UECC) errors.
Innovation Solution
The implementation of latch circuits such as dual interlocked storage cell (DICE) latches, static random access memory (SRAM) latches, and half interlock latch circuits, which offer varying levels of resistance to soft errors and chip area efficiency, including the use of cross-coupled CMOS inverters and series/parallel-connected transistors to manage current transfer and maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional latch circuitry is used to read fuse information, then the fuse bank can store data, but the latch circuitry occupies large area on the semiconductor chip, inhibiting increased fuse bank chip density
Solution Approach 1:
The latch circuit is divided into two separate half-latch circuits (first half-latch and second half-latch), each performing a portion of the latching function. This segmentation allows the circuits to be operated in an interlocked manner, achieving full latching functionality while reducing the area occupied by each individual circuit component compared to a traditional single latch circuit.
2Reliability
If traditional latch circuitry is used, then data can be read from fuses, but the large area occupation and circuit complexity increase the likelihood of soft errors from particle strikes
Solution Approach 1:
The interlocked half-latch configuration provides inherent error protection by requiring simultaneous state changes in both half-latches. This interlocking mechanism acts as a cushion against soft errors, as a particle strike affecting only one half-latch cannot cause a complete state transition, thereby preventing erroneous data output.
3Area of stationary object
If SRAM latches are used, then chip area is reduced for higher density, but vulnerability to soft errors increases
Solution Approach 1:
The invention creates a composite latch structure by combining elements of both traditional latches and SRAM-like efficiency. The interlocked half-latch configuration uses standard CMOS transistors arranged in a novel topology that achieves area efficiency comparable to SRAM while incorporating error-protection mechanisms that enhance reliability, thus combining the advantages of both approaches.
4Reliability
If half interlock latch circuits are used instead of SRAM latches, then resistance to soft errors is improved with higher critical charge requirement, but chip area occupation increases
Solution Approach 1:
The half-latch circuits are designed to be dynamically controlled through clock signals and control nodes, allowing them to switch between storage and transfer modes. This dynamic operation enables the circuits to achieve higher error resistance when needed while maintaining area efficiency through optimized transistor sizing and configuration that adapts to the operational requirements.
Data Source
AI summary
Fuse latch circuits and related systems, methods, and apparatuses are disclosed. An apparatus includes a half interlock latch circuit including a first half and a second half. The first half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the second half of the half interlock latch circuit in a driven state. The second half of the half interlock latch circuit is configured to operate in a high impedance state responsive to operation of the first half of the half interlock latch circuit in a driven state.