Half Latch Level Shifting Circuit for Non-Volatile Memory
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently managing signal voltages across memory cells, leading to inefficiencies in read and write operations, particularly in multi-deck non-volatile memory architectures where precise voltage thresholds are crucial for accurate data storage and retrieval.
Innovation Solution
The implementation of a half latch level shifting circuit that modifies low voltage signals into higher voltage signals, allowing for effective address decoding and reduced transistor count, thereby improving address line access speed and reducing die size while enhancing operational margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional level shifting circuits are used in multi-deck non-volatile memory architectures, then voltage control is achieved, but transistor count and die size increase
Solution Approach 1:
The patent extracts the level shifting function from traditional circuits and implements it using a half latch circuit configuration. By taking out unnecessary circuit components and retaining only the essential half latch structure, the design achieves voltage control with reduced transistor count, directly resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent changes the operational parameters of the half latch circuit by applying specific voltage levels (VBL, VBLB, VBLH) to control the p-channel and n-channel transistors. This parameter-based control enables precise voltage shifting while maintaining a minimal transistor count, addressing both voltage control accuracy and circuit simplicity requirements.
2Measurement precision
If more transistors are used for precise voltage control, then voltage threshold accuracy improves, but die size increases
Solution Approach 1:
The patent extracts only the necessary transistor components needed for voltage threshold control, implementing a half latch circuit that uses minimal transistors while maintaining precise voltage control. This extraction approach reduces die size while preserving measurement precision for voltage thresholds.
Solution Approach 2:
The patent segments the voltage control function into distinct half latch circuits for different voltage levels (VBL, VBLB, VBLH). Each segment handles specific voltage control tasks independently, allowing precise voltage threshold control without requiring a monolithic large transistor array, thus reducing overall die size.
3Ease of operation
If conventional address decoding circuits are used, then address signals are decoded, but access speed decreases
Solution Approach 1:
The patent implements dynamic control of the half latch circuits by enabling them based on partition select signals. This dynamic activation allows address decoding to occur only when needed, improving access speed by eliminating unnecessary static circuit delays while maintaining full address decoding functionality when activated.
Solution Approach 2:
The patent prepares the half latch circuits in advance by pre-configuring the p-channel and n-channel transistor networks for different voltage levels. This preliminary setup allows rapid address signal decoding when access is required, improving speed while maintaining the necessary decoding functionality through pre-established circuit pathways.
4Reliability
If full latch circuits are used for level shifting, then voltage control is achieved, but transistor count doubles
Solution Approach 1:
The patent extracts the essential voltage control function from complete latch circuits, retaining only the half latch configuration. This extraction removes redundant transistors while preserving the core voltage control capability, achieving reliable voltage control with half the transistor count of conventional latch circuits.
Solution Approach 2:
The patent applies partial action by implementing only the necessary half latch functionality rather than complete latch circuits. This partial implementation provides sufficient voltage control for the memory architecture while avoiding the excessive transistor count that would result from using full latch circuits, directly resolving the contradiction between reliability and device complexity.
Data Source
AI summary
A memory device may include a level shifter circuit that drives multiples half latch circuits. The half latch circuits may each include a p-channel transistor whose source is connected to a first voltage and whose gate is to receive addressing signals, a first inverter circuit connected between the drain of the p-channel transistor and a second voltage and whose input is connected to an output of the level shifter circuit, a second inverter circuit connected between the second voltage and a third voltage to receive an output of the first inverter circuit as input, a third inverter circuit connected between the second and third voltages to receive an output of the second inverter circuit as input, and an n-channel transistor connected between the output of the third inverter circuit and the input of the second inverter circuit, wherein a gate of the n-channel transistor is connected to a bias voltage.