Half-Page Memory Modes for Power and Parity
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Solution Overview
Problem
There is a need to improve the efficiency of memory devices and memory modules by reducing power consumption and allowing for additional information to be stored, particularly in modes where less than all memory cells are accessed at once.
Innovation Solution
The implementation of half-page modes in memory devices, where each word line is divided into separately addressed portions, allows for power savings by activating only the necessary portions of the word line during access operations. Additionally, module parity bits are stored on data memory devices instead of dedicated error correction memory devices, optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all memory cells are accessed at once, then data access speed is maximized, but power consumption increases and additional information cannot be stored
Solution Approach 1:
The patent divides each word line into two separately addressable portions (first and second portions), allowing the memory device to selectively activate only the necessary portion during access operations. This segmentation enables half-page mode operation where only half of the memory cells need to be accessed at once, reducing power consumption while maintaining data access capability. The row driver selectively activates either the first or second portion based on the row address, achieving energy efficiency without sacrificing productivity.
2Reliability
If dedicated error correction memory devices are used, then reliability is improved, but device complexity and resource utilization deteriorate
Solution Approach 1:
The patent merges the function of dedicated error correction memory devices with data memory devices by storing module parity bits in the same memory array. Instead of using separate devices for error correction, the system combines data storage and parity storage in a unified memory structure, reducing device complexity and improving resource utilization while maintaining reliability through integrated error correction capability.
Solution Approach 2:
The memory device achieves multi-functionality by using the same memory array for both data storage and error correction code storage. The memory cells serve dual purposes: storing user data during normal operations and storing module parity bits for error correction when needed. This universal usage of memory resources eliminates the need for dedicated error correction memory devices while preserving reliability.
3Quantity of substance
If additional information is stored separately, then information capacity increases, but access time and burst length increase
Solution Approach 1:
The patent segments the memory array into data storage regions and additional information storage regions within the same word line portions. By dividing each word line into two addressable portions, the system can store data in one portion and additional information (module parity bits, metadata) in the other portion, both accessible during the same access operation. This segmentation enables increased information capacity without extending access time or burst length.
Solution Approach 2:
The system performs preliminary organization of memory cells into separately addressable portions, preparing the structure in advance to allow simultaneous access to both data and additional information. By pre-configuring the memory array with distinct addressable regions, the system enables parallel retrieval of data and additional information during a single access operation, avoiding time loss that would result from sequential access.
Data Source
AI summary
Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.