Half-Page Memory Word Line Segmentation for Power and Parity
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Solution Overview
Problem
There is a need to improve the efficiency of memory devices and memory modules to reduce power consumption and allow for additional information storage, particularly in accessing and utilizing non-accessed bits in memory modes.
Innovation Solution
The implementation of half-page modes in memory devices, where each word line is divided into separately addressed portions, allows for power savings by activating only the necessary portions of the word line during access operations. Additionally, module parity bits are stored on data memory devices, eliminating the need for error correction memory devices, and additional information such as metadata is transmitted in parallel with data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all word line portions are activated during access operations, then maximum data access speed is achieved, but power consumption increases
Solution Approach 1:
The word line is divided into multiple separately-addressable portions (first portion and second portion), allowing selective activation of only the required segment during access operations. This segmentation enables the system to maintain fast access speeds for the active portion while avoiding power consumption from activating unnecessary portions.
Solution Approach 2:
Instead of activating the entire word line, the system activates only the partial portion that contains the target memory cells. This partial action approach achieves the necessary data access functionality while reducing overall power consumption by leaving other portions in an inactive state.
2Reliability
If error correction memory devices are used, then data reliability is improved, but device complexity and resource utilization increase
Solution Approach 1:
The patent merges the error correction functionality into the existing data memory devices by implementing separate addressable portions. Each data memory device can independently manage its own error correction for its first and second portions, eliminating the need for dedicated error correction memory devices and reducing overall system complexity.
Solution Approach 2:
Data memory devices are given multi-functionality by enabling them to perform both data storage and error correction operations. The same memory infrastructure handles both primary data and error correction data, making the system more resource-efficient while maintaining reliability.
3Ease of operation
If only data bits are accessed, then access operation simplicity is maintained, but additional information such as metadata cannot be stored
Solution Approach 1:
The memory word line is segmented into first and second portions, where the first portion stores data bits and the second portion stores additional information such as metadata. This segmentation allows both data and metadata to be accessed during the same operation while maintaining the simplicity of a unified access interface.
Solution Approach 2:
The system adds an additional dimension to the storage capability by utilizing the second portion of the word line for metadata storage. This dimensional expansion allows the memory to simultaneously handle both data and additional information without complicating the basic access operation interface.
Data Source
AI summary
Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.