Half-Pipe Nanosheet Gate Structure for Vertical Fin Spacing
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Solution Overview
Problem
Field-effect transistors with vertical fins face challenges in maintaining proper operation due to small intervals between adjacent fins, leading to performance issues.
Innovation Solution
A semiconductor device with a channel sheet having a half-pipe structure and a gate layer covering portions of the channel sheet, enhancing the contact area between the channel and gate layers through a gate-all-around (GAA) configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If vertical fins are used to increase effective conduction width, then the conduction capability is improved, but the interval between adjacent fins becomes too small to operate properly
Solution Approach 1:
The patent transitions from traditional planar FinFET structures to a 3D nanosheet configuration where multiple thin sheet-like channel structures are stacked vertically. This dimensional change allows the channel to wrap around the gate in multiple directions, achieving gate-all-around control while maintaining sufficient spacing between adjacent channel structures for proper operation.
Solution Approach 2:
The gate structure completely surrounds each nanosheet channel from all directions (gate-all-around configuration), with multiple nanosheets nested vertically above each other. This nesting approach maximizes the gate's control over the channel while maintaining compact layout and adequate spacing between individual channel elements.
2Reliability
If the contact area between channel and gate is increased to improve gate controllability, then the gate control is enhanced, but the device complexity increases
Solution Approach 1:
The channel is divided into multiple discrete thin nanosheet segments stacked vertically, each independently surrounded by the gate. This segmentation increases the total contact area between gate and channel, improving gate controllability while keeping each individual nanosheet simple in structure and easy to manufacture.
Data Source
AI summary
A semiconductor device according to an embodiment of the present disclosure includes a first channel sheet located over a lower structure and extending in a first direction, a gate layer covering a portion of the first channel sheet when coinciding with the first channel sheet in a second direction, the second direction being perpendicular to the first direction, and a gate insulating layer located between the first channel sheet and the gate layer, wherein the first channel sheet has a half-pipe structure including a curved surface in the second direction.