Half-Precision Floating-Point Array Multiplication with Segmented Accumulation
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Solution Overview
Problem
Existing multiplier circuits face inefficiencies in performing matrix multiplications and MAC operations, particularly in terms of speed and hardware requirements, especially when dealing with high-precision floating-point data, which increases costs and processing time.
Innovation Solution
The integration of an accumulator facility, such as a new register file or partitioned register file, that allows for parallel execution and storage of outer products during MAC operations, enabling reduced precision (e.g., 16-bit) multiplications while maintaining acceptable accuracy for applications like machine learning, by utilizing a processor with multiple execution blocks to generate and accumulate vectors in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-precision floating-point multiplication is performed, then accuracy is improved, but processing speed deteriorates and hardware complexity increases
Solution Approach 1:
The patent divides the multiplication operation into two stages: first performs lower-precision multiplication to generate initial product bits, then performs higher-precision multiplication on selected portions to generate final product bits. This segmentation allows the system to achieve high accuracy while maintaining fast processing speed by avoiding full high-precision computation for all bits simultaneously.
Solution Approach 2:
The patent performs preliminary lower-precision multiplication first to generate initial product bits before performing the final higher-precision multiplication. This preliminary action provides a foundation that reduces the complexity of the subsequent high-precision operation, enabling faster overall processing while maintaining accuracy.
2Productivity
If additional hardware is implemented to accelerate arithmetic operations, then processing speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent employs dynamic selection logic that determines which multiplication operations require higher precision based on the values of input operands. The circuit adaptively switches between lower-precision and higher-precision multiplication paths, optimizing hardware utilization and reducing the need for dedicated high-precision hardware for all operations.
Solution Approach 2:
The patent changes the precision parameter of multiplication operations based on input conditions. By dynamically adjusting the precision level according to operand values and required accuracy, the system achieves high processing speed with reduced hardware complexity, as full high-precision hardware is not required for all operations.
3Device complexity
If reduced precision multiplication is used, then hardware requirements are reduced, but accuracy deteriorates
Solution Approach 1:
The patent segments the multiplication result into initial product bits (from lower-precision multiplication) and final product bits (from higher-precision multiplication). By selectively applying higher-precision multiplication only where needed, the system achieves accurate results while using simplified hardware for the majority of computation.
Solution Approach 2:
The patent uses lower-precision multiplication as an intermediary step to generate initial product bits, which then serve as input or reference for the higher-precision multiplication stage. This intermediary approach allows the system to bridge between simplified hardware operations and high-accuracy requirements.
Data Source
AI summary
Methods and systems of matrix multiplication are described. In an example, a processor can multiply a first entry of a first vector of a first data array with a second vector of a second data array to generate a third vector of a third data array. The processor can store the third vector of the third data array in the second register file. The processor can multiply a second entry of the first vector with the second vector to generate a fourth vector of the third data array. The processor can store the fourth vector of the third data array in the second register file. The processor can combine vectors of the third data array that are stored in the second register file to produce the third data array.