Half-Rate CDR Circuit for Low-Power Jitter Reduction
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Solution Overview
Problem
Existing full-rate clock and data recovery (CDR) circuits consume more power due to their design, which is not efficient for high-speed transceivers, and they suffer from data-dependent jitter and duty cycle sensitivity issues.
Innovation Solution
A linear, half-rate CDR circuit design that includes a phase detector with latches clocked by both edges of the clock signal, a summing circuit generating a phase error signal, and a voltage-controlled oscillator (VCO) to align both edges of the clock signal with the baud center of the data signal, reducing power consumption and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If full-rate CDR circuit is used, then clock signal frequency is high enough to align with data rate, but power consumption increases significantly
Solution Approach 1:
The patent uses periodic action by implementing a half-rate CDR circuit that operates at half the frequency of full-rate circuits. The phase detector and VCO are designed to update and adjust parameters periodically at half-rate, maintaining necessary clock recovery functionality while reducing power consumption proportional to the square of the frequency reduction.
2Measurement precision
If full-rate CDR circuit is used, then clock recovery accuracy is sufficient, but data-dependent jitter is generated
Solution Approach 1:
The patent extracts and eliminates the data-dependent jitter component by using a half-rate phase detector that samples transitions at half the data rate. This extraction approach removes the harmful jitter effect while preserving the essential clock recovery function through periodic updates at half-rate.
3Adaptability or versatility
If full-rate CDR circuit is used, then clock signal can track data rate variations, but duty cycle sensitivity increases
Solution Approach 1:
The patent applies periodic action by updating the VCO control parameters at half-rate intervals rather than continuously at full-rate. This periodic update mechanism maintains the ability to track data rate variations and adapt to duty cycle changes while reducing sensitivity to duty cycle distortion through the lower update frequency.
Data Source
AI summary
A linear, half-rate clock and data recovery (CDR) circuit for recovering clock information embedded in a received data signal. The half-rate CDR circuit comprises a phase detector that may receive the data signal and generate a phase error signal representative of the phase difference between the received data signal and a clock signal produced by a voltage-controlled oscillator (VCO) of the CDR circuit. The half-rate CDR typically changes the frequency of the clock signal and generates a clock signal that is aligned with the baud center of the received data signal. More specifically, when the half-rate CDR circuit is in a locked condition, both the rising and falling edges of the clock signal are aligned with the baud center of the received data signal. The half-rate CDR preferably generates a clock signal with an average frequency that is half the data rate of a received data signal.