Half-Rate CDR Charge Pump Normalization for Lower Jitter
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Solution Overview
Problem
Existing clock and data recovery circuits face challenges in accurately extracting data from a data signal synchronized with a clock signal, due to the absence of the clock signal in the data transmission link, leading to difficulties in phase locking and increased jitter and power consumption.
Innovation Solution
A clock and data recovery circuit incorporating a phase detector, charge pump, and voltage controlled oscillator, where the phase detector generates phase difference signals and an OR gate is used to simplify the charge pump output, reducing complexity and power consumption, and improving the maximum operational speed by eliminating unnecessary multiplexers and normalization circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional charge pump circuits with multiple phase difference signals are used, then phase detection accuracy is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent combines multiple phase difference signals (UP1, UP2, DN1, DN2) from a half-rate CDR into a single normalized charge pump output signal. The OR gate logic merges the multiple UP signals and multiple DN signals, respectively, reducing the number of charge pump outputs while maintaining phase detection accuracy through the normalized gain approach.
Solution Approach 2:
The normalized charge pump circuit serves multiple functions: it handles phase detection for both UP and DN directions, normalizes the gain across different data transition densities, and provides a unified output signal format. This multi-functional design reduces overall circuit complexity while maintaining measurement precision.
2Reliability
If normalization circuitry is added to handle data transition density variations, then phase locking accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the operational parameters of the charge pump by dynamically adjusting its effective gain through OR gate logic. When multiple phase difference signals are active simultaneously (high data transition density), the OR gate prevents current doubling, effectively normalizing the charge pump output without requiring additional normalization circuitry or increased power consumption.
Solution Approach 2:
The patent extracts the normalization function from separate normalization circuitry and integrates it directly into the charge pump's control logic through OR gates. This eliminates the need for additional normalization components while maintaining phase locking accuracy, thereby reducing power consumption.
3Speed
If complex charge pump output logic is used to handle all phase difference scenarios, then operational speed is improved, but device complexity increases
Solution Approach 1:
The OR gate logic is pre-configured to handle all possible phase difference signal combinations (UP1, UP2, DN1, DN2) simultaneously. This preliminary design ensures that regardless of the data transition density or phase error direction, the charge pump output is immediately normalized without requiring complex real-time decision logic, thus maintaining high operational speed with simple circuitry.
Data Source
AI summary
A clock and data recovery circuit includes a phase detector circuit, a charge pump circuit, and a voltage controlled oscillator. The phase detector circuit receives a data signal from an external device and a clock signal from the voltage controlled oscillator and generates a first and a second phase difference signal. The charge pump circuit includes an OR gate receiving on its inputs the first and the second phase difference signals and configured to generate a current if the first and/or second phase difference signal is high.