Half-Rate Clock Data Recovery Using Programmable Feedback
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Solution Overview
Problem
Existing C-PHY clock and data recovery (CDR) designs in receivers are limited by internal closed loop timing relationships and depend on delay line phase and frequency detection, which are prone to nonlinear effects and environmental variations, limiting their performance as signaling frequencies increase.
Innovation Solution
A method and apparatus that derive a first clock signal from a 3-wire, 3-phase interface and use a programmable generator in a delay loop to generate a second clock signal with a lower frequency, fed back to the data input of a flip-flop logic, allowing for improved clock recovery independent of delay line phase and frequency detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay line phase and frequency detection is used in CDR designs, then clock recovery can be achieved, but performance is limited by nonlinear effects and environmental variations at higher signaling frequencies
Solution Approach 1:
The patent segments the clock recovery function into multiple independent components: a first flip-flop for edge detection, a second flip-flop for phase comparison, and a delay element for timing adjustment. This segmentation eliminates the need for complex delay line phase detection while improving reliability at high frequencies by reducing the impact of environmental variations on any single component.
Solution Approach 2:
Instead of using traditional delay line phase detection that is sensitive to environmental variations, the patent inverts the approach by using a feedback mechanism where the recovered clock is delayed and compared with the original data. This inversion allows the system to adapt to environmental changes dynamically, improving measurement precision without complex delay line calibration.
2Measurement precision
If delay circuits are used to ensure stable signaling states before sampling, then sampling accuracy is improved, but transmission rate is limited by the delay values
Solution Approach 1:
The patent implements dynamic timing adjustment by using a delay element whose value can be optimized for different transmission rates. The delay is applied to the recovered clock signal in a feedback loop, allowing the system to maintain sampling accuracy across a wide range of transmission rates without being limited by fixed delay values. This dynamic approach enables higher productivity while preserving measurement precision.
3Reliability
If closed loop timing relationships are used in CDR designs, then clock recovery is achieved, but the design is heavily dependent on delay line accuracy which varies with process, temperature, and channel length
Solution Approach 1:
The patent employs feedback by delaying the recovered clock signal and using it to control the sampling timing. This feedback mechanism allows the system to automatically compensate for environmental variations such as process, temperature, and channel length changes. The delay element in the feedback loop adjusts the timing dynamically, improving adaptability while maintaining reliable clock recovery across different operating conditions.
Solution Approach 2:
The patent changes the parameter being controlled from delay line phase detection to a feedback-based timing mechanism. By using a delay element in the feedback path rather than in the forward path, the system becomes less sensitive to environmental variations. The parameter adjustment is done dynamically through the feedback loop, enhancing adaptability to different operating conditions while maintaining reliable performance.
Data Source
AI summary
Data communication apparatus and methods for a multi-wire interface are disclosed. A half rate clock and data recovery (CDR) circuit derives a clock signal including pulses corresponding to symbols transmitted on a 3-wire interface, where the symbols are transmitted at a particular frequency with each of the symbols occurring over a unit interval (UI) time period. The first clock signal is input to a flip-flop logic included in a delay loop, and serves to trigger the first flip-flop logic. A second clock signal is generated using a programmable generator in the delay loop and has a frequency of a half UI and is fed back to a data input of the flip-flop. The output of the flip-flop is used as a recovered clock signal for the CDR at a half rate frequency. This design provides ease of timing control, a delay line without extra nonlinear-effects, and less hardware overhead.