Half-Rate Clock Recovery Circuit for High-Speed C-PHY Signals
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Solution Overview
Problem
Existing clock recovery methods in high-speed communication environments face limitations in reducing delay time, accuracy, and power consumption, particularly in C-PHY receivers, which affect the efficiency and precision of clock signal recovery.
Innovation Solution
A signal receiving circuit employing a half-rate clock recovery method using a loop interruption circuit and delay circuit, comprising pulse generators and transistors, to generate recovery clock signals and delay signals, minimizing unnecessary delay and optimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-rate clock recovery method is used, then one rising edge corresponds to each received symbol, but additional time delay is needed and maximum operating speed is limited
Solution Approach 1:
The patent uses half-rate clock recovery where one rising or falling edge corresponds to each symbol, reducing the periodic requirement from full-rate to half-rate operation. This allows the clock signal to be generated at half the symbol rate, eliminating the need for additional delay circuits while maintaining recovery accuracy through edge detection of both rising and falling transitions.
2Speed
If communication speed increases, then symbol interval decreases, but delay time reduction is limited and accuracy and efficiency of clock signal recovery are lowered
Solution Approach 1:
The patent employs a feedback mechanism where the recovered clock signal is used to control the timing of symbol sampling. By detecting edges in the received signal and generating clock transitions accordingly, the system adapts to varying communication speeds while maintaining synchronization accuracy through continuous feedback from the received signal characteristics.
3Reliability
If conventional clock recovery circuits are used, then clock signal recovery function is performed, but circuit area and power consumption are increased
Solution Approach 1:
The patent extracts only the essential functionality needed for clock recovery by using simple edge detection circuits and pulse generators instead of complex phase-locked loops or delay-locked loops. This extraction of core functions eliminates unnecessary circuit components, significantly reducing circuit area and power consumption while maintaining reliable clock signal recovery capability.
Data Source
AI summary
Provided is a signal receiving device that receives first to third input signals, each having a different signal level at each unit interval (UI). The device includes: first to N-th clock recovery modules operating in a half-rate clock recovery method; and a logic operation unit for performing logic operation on the recovery clock signal output from the first to N-th clock recovery modules and outputting the recovery clock signal. The first to N-th clock recovery modules generate a recovery clock delay signal obtained by delaying the recovery clock signal as much as a first delay time. The first delay time is larger than the unit interval. The first to N-th clock recovery modules are sequentially enabled at each unit interval.