Half-Rate Decision Feedback Equalizer for ISI Reduction
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Solution Overview
Problem
The limited bandwidth of interconnects in digital computing systems leads to broadened pulses and severe Inter-Symbol Interference (ISI), making high-speed data transmission challenging due to the low pass nature of the channel, necessitating high-speed equalization circuitry.
Innovation Solution
A decision feedback equalizer (DFE) is implemented, comprising a summer, a slicer, and a feedback circuit, where the slicer operates at a half-rate clock, and the feedback circuit generates a correction signal to improve signal recovery, utilizing inverter-based summer and track-based slicer topology for power efficiency and higher bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed data transmission is implemented through interconnects, then data rate increases, but pulse broadening and Inter-Symbol Interference worsen due to limited bandwidth
Solution Approach 1:
The patent implements a decision feedback equalizer that uses feedback from previously detected symbols to generate correction signals. The feedback circuit processes past decisions and feeds correction signals back to compensate for ISI, allowing high-speed transmission while maintaining signal quality through continuous adaptive correction
Solution Approach 2:
The equalizer performs preliminary equalization of the input signal before slicing by adding correction signals that pre-compensate for expected ISI. This preliminary action removes distortion before the critical detection stage, enabling reliable high-speed data recovery
2Measurement precision
If traditional full-rate slicing is used, then signal recovery accuracy is maintained, but power consumption and timing constraints increase
Solution Approach 1:
The patent employs alternating slicing where two slicers operate on alternating clock cycles at half the data rate. This periodic operation reduces the switching activity and power consumption of the slicers while maintaining full-rate signal recovery accuracy through the complementary operation of multiple slicers
Solution Approach 2:
The slicing function is segmented into multiple slicers operating at reduced clock rates. Instead of one full-rate slicer, multiple half-rate slicers divide the workload, reducing individual power consumption while collectively maintaining full data rate accuracy through their combined output
3Reliability
If equalization circuitry is added to compensate for ISI, then signal quality improves, but device complexity increases
Solution Approach 1:
The patent combines the equalization and slicing functions into an integrated decision feedback equalizer structure. The summer, feedback circuit, and slicers are merged into a unified architecture that performs both equalization and detection in a coordinated manner, reducing overall system complexity compared to separate equalization and detection stages
Data Source
AI summary
A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.