Half-Rate Decision Feedback Equalizer Power Reduction
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Solution Overview
Problem
Half-rate decision feedback equalizers in high-speed data transmission systems face challenges of high power consumption and large size due to the use of multiple acquisition components, which are not effectively addressed by existing solutions.
Innovation Solution
A decision feedback equalizer comprising two decision sampling circuits operating with opposite sampling clock signals, where each circuit determines a correction mode based on previous sampling results to correct sampling data, reducing the need for multiple acquisition components and thereby lowering power consumption and circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a half-rate decision feedback equalizer uses multiple acquisition components to handle odd and even channels separately, then the sampling frequency can be reduced to half of the data stream frequency, but the power consumption and circuit area increase significantly
Solution Approach 1:
The patent merges the odd channel and even channel processing into a unified half-rate decision feedback equalizer structure. By using a single acquisition component that processes both channels through time-interleaved sampling, the design eliminates the need for separate acquisition components for each channel, thereby reducing power consumption while maintaining half-rate operation.
Solution Approach 2:
The acquisition component is designed to perform multiple functions by handling both odd and even channel sampling sequences. The same component alternates between sampling odd and even channels at different time intervals, making it a universal component that replaces what would traditionally require two separate components, thus reducing overall power consumption.
2Speed
If a half-rate decision feedback equalizer uses multiple acquisition components to handle odd and even channels separately, then the sampling frequency can be reduced to half of the data stream frequency, but the circuit area increases
Solution Approach 1:
The patent merges the odd channel and even channel processing into a unified half-rate decision feedback equalizer structure. By using a single acquisition component that processes both channels through time-interleaved sampling, the design eliminates the need for separate acquisition components for each channel, thereby reducing circuit area while maintaining half-rate operation.
Solution Approach 2:
The acquisition component is designed to perform multiple functions by handling both odd and even channel sampling sequences. The same component alternates between sampling odd and even channels at different time intervals, making it a universal component that replaces what would traditionally require two separate components, thus reducing overall circuit area.
3Reliability
If a full-rate decision feedback equalizer is used to eliminate Inter-Symbol Interference, then the signal integrity is improved, but the time sequence design requirements become very strict, causing increased design cost and difficulty
Solution Approach 1:
The patent changes the sampling rate parameter from full-rate to half-rate operation. By sampling at half the data stream frequency and using time-interleaved processing for odd and even channels, the system maintains signal integrity for ISI elimination while relaxing the time sequence design requirements, thereby reducing design complexity and cost.
Data Source
AI summary
The present disclosure discloses a decision feedback equalizer and a method for acquiring and correcting data. The decision equalizer comprises: a first decision sampling circuit; and a second decision sampling circuit; wherein an input end of the first decision sampling circuit is configured to receive sampling data and a first sampling result outputted by the second decision sampling circuit in a previous sampling period; and an input end of the second decision sampling circuit is configured to receive sampling data and a second sampling result outputted by the first decision sampling circuit in a previous sampling period.


