Half-Rate PWM Demodulation Without PLLs for Jitter Tolerance
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Solution Overview
Problem
High-performance PWM transceiver systems face challenges with jitter tolerance due to the need for power-hungry clock recovery circuits and phase locked loops, which increase power consumption and chip area, and require additional bit streams for synchronization.
Innovation Solution
A low-power PWM receiver design that employs a half-rate demodulation scheme, eliminating the need for DLLs or PLLs and sync-bits, using a voltage level shifter, half-rate PWM decoder, and deserializer to accommodate jitter and reduce power consumption across a wide data rate range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock recovery circuits and phase locked loops are used for high-performance PWM transceiver systems, then jitter tolerance is improved, but power consumption and chip area increase
Solution Approach 1:
The patent extracts and eliminates the clock recovery circuit and phase locked loop from the receiver system. Instead of using these complex synchronization circuits, the invention uses a simplified approach where the receiver directly samples the PWM signal at its input node, removing the power-hungry clock recovery blocks while maintaining acceptable jitter tolerance through the inherent sampling mechanism
Solution Approach 2:
The patent creates a simplified copy of the clock signal by generating a local clock at the receiver that runs at half the PWM data rate. This local clock is derived from the PWM signal itself rather than requiring an external high-precision clock source, reducing power consumption while maintaining synchronization
2Reliability
If clock recovery circuits and phase locked loops are used for high-performance PWM transceiver systems, then jitter tolerance is improved, but chip area increases
Solution Approach 1:
The patent removes the phase locked loop and delay locked loop circuits from the receiver architecture. By using direct sampling at the input node and a simplified half-rate decoding approach, the invention eliminates these large-area synchronization circuits while maintaining functional performance
Solution Approach 2:
The patent replaces complex, area-intensive PLL/DLL circuits with simpler, smaller components that can be implemented with fewer transistors. The local clock generator and direct sampling approach use minimal circuitry compared to traditional synchronization circuits
3Measurement precision
If additional bit stream for bit synchronization is used, then data recovery accuracy is improved, but device complexity increases
Solution Approach 1:
The patent removes the requirement for additional synchronization bit streams from the system. Instead of adding these extra data channels, the invention achieves data recovery by directly sampling the existing PWM signal and using a simplified decoding process that does not require separate sync bits
Solution Approach 2:
The patent makes the PWM signal serve multiple functions simultaneously. The same PWM signal is used for both data transmission and synchronization purposes, eliminating the need for separate sync bit streams. The half-rate decoding process extracts both timing and data information from the single PWM channel
Data Source
AI summary
A receiver for demodulating a pulse width modulated (“PWM”) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.