Half-Size Product Code Array Layout for Lower-Cost Parity Encoding
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Solution Overview
Problem
Conventional hardware implementations of half product code (HPC) encoders and decoders face challenges due to the high cost of integrated circuitry required for accessing data in both row and column formats, and the need for independent encoding of rows and columns, which does not leverage array symmetry, leading to inefficiencies in data processing.
Innovation Solution
A hardware-based encoder utilizing a binary symmetry-invariant product code, such as a half product code, is implemented with a half-size data array that allows iterative encoding by accessing bits from a reduced number of rows and columns, using shift register latches and rotating bits to generate parity, thereby reducing the complexity and cost of logic required for encoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full HPC array is used for encoding, then complete row and column data can be accessed, but the integrated circuitry cost and device complexity increase significantly
Solution Approach 1:
The patent extracts only the essential data elements needed for encoding by using a half-size data array that stores only one triangular portion of the HPC array. By removing the redundant symmetric portion, the system achieves complete encoding functionality with reduced hardware complexity and lower integrated circuitry cost while maintaining encoding accuracy.
Solution Approach 2:
The patent segments the full HPC array into two symmetric triangular portions and utilizes only one segment (the lower triangular portion including the diagonal). This segmentation allows the encoder to process data in a compressed format, reducing the required circuitry while maintaining the ability to generate correct row and column parities through iterative encoding.
2Reliability
If independent encoding of rows and columns is performed, then complete product code functionality is achieved, but the encoding process becomes less efficient
Solution Approach 1:
The patent merges the row and column encoding operations into a unified iterative encoding process that operates on the half-size data array. By combining these operations and exploiting the symmetry property where the lower triangular portion contains all necessary information, the system achieves both complete product code functionality and improved encoding efficiency.
3Device complexity
If a half-size data array is used, then logic complexity is reduced, but data access patterns become more complex
Solution Approach 1:
The patent implements dynamic data access mechanisms including shift register latches and rotating bit positions that adaptively retrieve data from the half-size array. These dynamic structures automatically handle the complex access patterns required by the compressed format, making the access mechanism transparent to the encoding logic while maintaining reduced device complexity.
Data Source
AI summary
An encoder encodes input data utilizing a binary symmetry-invariant product code. The encoder includes circuitry including a half-size data array including D rows each having storage for H data bits (D=2×H+1). The encoder is configured to access bits of each row of the product code by reading a first H-bit data word from one of the D rows and a second H-bit data word across H different rows of the half-size data array. The encoder additionally includes a register configured to receive the bits of each row of the product code and to rotate the bits to obtain the rows of the product code and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate, based on the row parity, column parities for the parity bits of all rows of the product code.