Half-Size HPC Encoder Layout for Single-Cycle Row Access
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Solution Overview
Problem
Conventional hardware implementations of half product code (HPC) encoders and decoders are costly due to the need for integrated circuitry that enables access in both row and column formats, and they do not benefit from array symmetry, making efficient encoding and decoding in hardware challenging.
Innovation Solution
A hardware-based encoder utilizing a binary symmetry-invariant product code, such as a half product code, is implemented with a half-size data array where input data is packed to have an equal number of bits in each row, allowing for efficient parity calculation and reduced logic requirements, enabling high-performance encoding and decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full-size HPC array is formed in memory with integrated circuitry for row and column access, then encoding and decoding can be performed, but the die area cost becomes very expensive
Solution Approach 1:
The patent extracts and eliminates the redundant symmetrical duplicate data from the HPC array. By recognizing that only one triangular portion of the symmetric array needs to be stored and processed, the implementation reduces the memory array size from N×N to approximately N×N/2, directly reducing die area while maintaining full encoding and decoding capability through software-based iterative decoding algorithms.
Solution Approach 2:
The patent inverts the conventional approach by using software-based iterative decoding instead of dedicated hardware circuitry for column access. This inversion allows the system to achieve the same decoding functionality without requiring expensive integrated circuitry for dual row-column access, thereby reducing die area costs.
2Quantity of substance
If a full-size HPC array is formed in memory, then complete data can be stored, but the logic complexity increases
Solution Approach 1:
The patent extracts and removes the redundant symmetrical duplicate data from the HPC array structure. By storing only one triangular portion of the symmetric array and using software algorithms to generate the other portion during decoding, the system maintains complete data storage capacity while reducing logic complexity and memory requirements.
3Productivity
If hardware implementation is used for high performance, then encoding speed improves, but the cost of integrated circuitry for dual row-column access becomes very expensive
Solution Approach 1:
The patent replaces the mechanical/hardware system (integrated circuitry for column access) with a software-based iterative decoding system. This substitution maintains high encoding and decoding performance while dramatically reducing manufacturing costs by eliminating the need for complex dual row-column access circuitry, relying instead on programmable logic or general-purpose processors.
Data Source
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AI summary
An encoder encodes input data utilizing a binary symmetry-invariant product code. The encoder includes circuitry including a half-size data array including D rows each having storage for H data bits (D=2×H+1). The encoder is configured to access bits of each row of the product code by reading a first H-bit data word from one of the D rows and a second H-bit data word across H different rows of the half-size data array. The encoder additionally includes a register configured to receive the bits of each row of the product code and to rotate the bits to obtain the rows of the product code and a row parity generator configured to generate row parity for each row of the product code. The encoder finally includes a column parity generator configured to generate, based on the row parity, column parities for the parity bits of all rows of the product code.