Half-tone Mask Patterning for a-Si OLED Array Substrates
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Solution Overview
Problem
The manufacturing process for amorphous silicon (a-Si) array substrates in low-definition OLED displays is complex and costly, as it typically requires 9 to 13 masks, similar to those used for low-temperature poly-silicon (LTPS) substrates, leading to high production costs.
Innovation Solution
A method is proposed that reduces the number of masks required by patterning a gate metal and pixel electrode with a first half-tone mask, a gate insulation and semiconductor layer with a second half-tone mask, forming source/drain metallic layers with a third mask, and creating a bank layer with a fourth mask, using techniques such as sputtering, thermal evaporation, and chemical vapor deposition (CVD) to minimize the number of manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If 9 to 13 masks are used for patterning a-Si array substrates, then manufacturing precision is improved, but device complexity and production cost increase
Solution Approach 1:
The patent combines multiple patterning operations into a single exposure step using a half-tone mask. Specifically, the half-tone mask enables simultaneous patterning of the gate electrode, source electrode, and drain electrode in one step, whereas traditionally these would require separate masking steps. This merging of operations reduces the total mask count from 9-13 masks down to just 4 masks, directly resolving the contradiction between manufacturing precision and process complexity
Solution Approach 2:
The patent introduces a new dimension to the patterning process by using half-tone masks with varying optical densities (different gray levels). Instead of using multiple discrete masks for different patterns, the half-tone mask uses continuous variation in light transmission to create different etch depths and feature sizes in a single exposure. This dimensional approach to light intensity control enables complex multi-layer patterning with fewer masks
2Manufacturing precision
If 9 to 13 masks are used for patterning, then manufacturing precision is improved, but production cost increases
Solution Approach 1:
By merging multiple patterning functions into the half-tone mask, the patent eliminates the need to purchase, store, and handle 9-13 separate masks. The single half-tone mask performs the work of multiple traditional masks, directly reducing material costs and process costs associated with multi-mask operations
Solution Approach 2:
The half-tone mask creates optical copies of the desired patterns with varying intensities in a single exposure step. Different regions of the mask transmit different amounts of light to create the required pattern variations, eliminating the need for multiple physical mask copies and the associated costs
3Manufacturing precision
If multiple masking steps are used, then patterning precision is improved, but manufacturing time increases
Solution Approach 1:
The patent merges sequential patterning steps into a single parallel operation. The half-tone mask enables simultaneous definition of multiple electrodes and features in one exposure and development cycle, eliminating the sequential time required for multiple separate masking operations while maintaining the precision needed for each feature
Solution Approach 2:
The half-tone mask is designed in advance with pre-calculated optical density distributions that account for the desired final pattern geometry. This preliminary design of the mask's optical properties allows complex patterns to be formed directly in a single step without requiring multiple sequential adjustments or steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of masks needed to four, simplifying the manufacturing process and lowering production costs for a-Si array substrates in low-definition OLED displays.
Implementation Method 1
sputtering or thermal evaporating an indium tin oxide (ITO) pixel electrode layer
Implementation Method 2
sputtering or thermal evaporating an indium tin oxide (ITO) pixel electrode layer
Implementation Method 3
using chemical vapor deposition (CVD) to sequentially deposit the gate insulation layer
Data Source
AI summary
A method for manufacturing an array substrate for producing an amorphous silicon (a-Si) array substrate of a low-definition OLED display is provided. The method includes: patterning a gate metal and a pixel electrode on a glass substrate by using a first mask which is a first half tone mask; patterning a gate insulation layer and a semiconductor layer on the glass substrate with a second mask which is a second half tone mask; forming source/drain metallic layers and a channel with a third mask; and forming a bank layer with a fourth mask. The a-Si array substrates of low-definition OLED display panels undertake less manufacturing processes, which means that mask plates are used less and cost is reduced.