Low Power Half-VDD Circuit Using Transistor Pairs for Drive Capability

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Solution Overview

Problem

Existing common mode reference circuits in differential electronic circuits face challenges in achieving power efficiency, compact size, and stability across varying capacitive loads, particularly in ultralow power applications, where they often consume excessive current and occupy large areas.

Innovation Solution

The proposed solution involves a common mode reference circuit design utilizing a divider stage with n-channel and p-channel field effect transistor pairs connected in series to high and low supply voltage nodes, coupled with an output stage featuring current mirrors to enhance drive ability and stability, allowing for efficient power usage and compact design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a unity gain buffer is used to enhance drive ability, then the driving capability is improved, but the power consumption increases significantly

Engineering Contradiction:

Improvedriving capabilityVSAvoidpower consumption

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The patent combines the voltage division function and the buffer amplification function into a single integrated circuit stage. The common mode reference circuit generates VDD/2 while simultaneously providing enhanced drive capability through the unified transistor pair configuration, eliminating the need for separate buffer circuits and reducing overall power consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The transistor pairs in the common mode reference circuit serve multiple functions: they act as voltage dividers to generate VDD/2, provide buffer amplification for drive capability, and maintain circuit stability. This multi-functionality eliminates the need for separate dedicated buffer circuits, thereby reducing power consumption while maintaining driving capability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If resistors are chosen to limit current to 100 nA, then the power consumption is reduced, but the resistor area becomes very large

Engineering Contradiction:

Improvepower consumptionVSAvoidresistor area

Core Design Contradiction:

Use of energy by moving objectVSArea of stationary object

Solution Approach 1:

The patent replaces the passive resistor-based voltage division approach with an active transistor pair configuration. The transistor pairs (NFET/PFET) actively regulate the voltage division and current flow, enabling precise VDD/2 generation with minimal current consumption (100 nA) without requiring large physical resistor areas.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Use of energy by moving object

If the common mode reference circuit is designed for ultralow power operation, then the power consumption is reduced, but the circuit stability across different capacitive loads becomes problematic

Engineering Contradiction:

Improvepower consumptionVSAvoidcircuit stability

Core Design Contradiction:

Use of energy by moving objectVSStability of the object's composition

Solution Approach 1:

The patent employs dynamically responsive transistor pairs that automatically adjust their operating characteristics based on the connected capacitive load. The NFET/PFET configuration provides adaptive current regulation that maintains stable VDD/2 output across varying load conditions while consuming only 100 nA, achieving both ultralow power operation and circuit stability.

Inventive Principle:

Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves power efficiency, compact size, and fast response times while maintaining circuit stability across different capacitive loads, making it suitable for ultralow power applications and reducing power consumption by up to 80% compared to traditional methods.

Implementation Method 1

a first n-channel field effect transistor and p-channel field effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node

Methodology Applied

Scientific EffectField Effect Transistor operation:

Implementation Method 2

a first field effect transistor (FET) connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair

Methodology Applied

Scientific EffectCurrent mirror effect:

Data Source

PatentUS10613569B2Low power half-VDD generation circuit with high driving capability

Publication Date: 2020.04.07 ANALOG DEVICES GLOBAL UNLTD

AI summary

A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.