Half-Word Memory Device Shared Redundant Column

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Solution Overview

Problem

Conventional memory devices with a half-word architecture require multiple redundant columns and wordline gating, increasing circuit area, complexity, and manufacturing costs.

Innovation Solution

A memory device with a half-word architecture that uses a single redundant column for column redundancy, eliminating the need for wordline gating and reducing circuit area and complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple redundant columns and wordline gating are used in conventional half-word architecture memory devices, then column redundancy repair capability is improved, but circuit area and complexity increase

Engineering Contradiction:
Improvecolumn redundancy repair capabilityVSAvoidcircuit area and complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the redundant column resources of left and right segments into a single shared redundant column. The shift control circuitry dynamically redirects bitlines from either segment to this unified redundant column, eliminating the need for separate redundant columns in each segment and reducing overall circuit area while maintaining repair capability for both halves of the memory device

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single redundant column is designed to serve multiple functions: it can repair faults in both the left and right segments of the memory array. The shift control circuitry enables this universal repair capability by dynamically connecting bitlines from either segment to the shared redundant column based on where faults are detected, making the redundant column a multi-functional resource

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If separate redundant columns are added to each segment (left and right), then fault coverage is improved, but manufacturing costs increase

Engineering Contradiction:
Improvefault coverageVSAvoidmanufacturing costs
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines what would traditionally be two separate redundant columns (one for left segment, one for right segment) into a single shared redundant column. This merging reduces the total number of transistors and circuit elements required, directly lowering manufacturing costs while the shift control circuitry ensures both segments remain covered for fault repair

Inventive Principle:
Principle #5Merging (Combining)

3Ease of operation

If wordline gating is implemented to control segments, then segment isolation is improved, but device complexity increases

Engineering Contradiction:
Improvesegment isolationVSAvoiddevice complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent extracts and removes the wordline gating mechanism from the system. Instead of using wordline gating to control segment access, the design relies on shift control circuitry that redirects bitlines to appropriate segments or the shared redundant column. This extraction eliminates the complexity of wordline gating while maintaining the ability to isolate and control segments through the shift control mechanism

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12340865B2Reduced circuit area memory device with a half-word memory architecture
Publication Date: 2025.06.24 SYNOPSYS INC
  • US12340865B2 patent drawing
  • US12340865B2 patent drawing
  • US12340865B2 patent drawing

AI summary

A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.