Half-Bridge Power Module Reducing Parasitic Inductance
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Solution Overview
Problem
The existing half-bridge power semiconductor modules fail to achieve intended reduction in parasitic inductance due to imperfect adjacent antiparallel conduction, leading to increased surge voltages and conduction losses.
Innovation Solution
The design includes an insulating substrate with surface and rear surface wiring conductors, connection conductors, and terminals that facilitate ohmic connections between power semiconductor devices, enhancing adjacent antiparallel conduction by ensuring opposite-direction current flow through the conductors, thereby reducing parasitic inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If adjacent antiparallel conduction is implemented in conventional power modules, then parasitic inductance reduction is intended, but imperfect conduction prevents achieving the intended reduction
Solution Approach 1:
The current path is segmented into multiple conductors arranged in pairs, with each pair carrying opposite-direction currents. The connection conductors are divided into first and second connection conductors that connect to different terminals, creating distinct current paths that can be optimized independently for perfect antiparallel conduction.
Solution Approach 2:
Different regions of the module are assigned different conductor configurations optimized for their specific functions. The connection conductors have specific arrangements that ensure opposite-direction current flow in adjacent regions, while terminal regions are designed for optimal current extraction, creating local quality variations that collectively achieve perfect antiparallel conduction.
2Ease of manufacture
If wiring structure is simplified for easier manufacture, then manufacturing ease is improved, but parasitic inductance reduction capability deteriorates
Solution Approach 1:
Multiple functions are merged into the connection conductors and wiring structure. The same conductors that provide electrical connections also serve as the antiparallel current paths for parasitic inductance reduction, eliminating the need for separate structures and simplifying manufacturing while achieving both goals.
Solution Approach 2:
The wiring structure is designed to perform multiple functions simultaneously: electrical connection, current distribution, and parasitic inductance reduction through antiparallel conduction. This multi-functionality reduces the overall complexity of the wiring system while maintaining performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic inductance across the module, minimizing surge voltages and conduction losses, and enhancing the performance of power semiconductor devices.
Implementation Method 1
an electromagnetic method for reducing the parasitic inductance of a wiring by feeding opposite-direction currents through the adjacently arranged reciprocating wirings (hereinafter, referred to as 'adjacent antiparallel conduction)' is applied
Implementation Method 2
A rear electrode of the low-side power semiconductor device is ohmically connected to a first surface-wiring conductor. A rear electrode of the high-side power semiconductor device is ohmically connected to a second surface-wiring conductor
Data Source
AI summary
A module (1) includes an insulating substrate (15), a power semiconductor device (13HT), a power semiconductor device (13LT), a bridge terminal (14B), a high-side terminal (14H), and a low-side terminal (14L). The bridge terminal extends from a surface wiring conductor (12B) at a position between the power semiconductor devices (13HT, 13LT). The high-side terminal extends from a high-side rear surface wiring conductor (17H) at a position between the power semiconductor devices (13HT, 13LT). The low-side terminal extends from a low-side rear surface wiring conductor (17L) at a position between the power semiconductor devices (13HT, 13LT). A surface electrode of the power semiconductor device (13HT) and a rear electrode of the power semiconductor device (13LT) are connected to the surface wiring conductor (12B).