Half-Bridge Semiconductor Switches for High Voltage Blocking
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Solution Overview
Problem
Conventional half-bridge circuits using semiconductor switches face limitations in voltage blocking capability and on-resistance, particularly when operating with high-voltage applications, as they rely on a single semiconductor device and lack efficient voltage distribution across multiple transistors.
Innovation Solution
The proposed solution involves a half-bridge circuit configuration with a first semiconductor switch and a second semiconductor switch, where the second semiconductor devices are connected in series and their control terminals are connected to each other and the first semiconductor device, forming a cascode-like circuit. This configuration enhances voltage blocking capability and reduces on-resistance by distributing voltage across multiple transistors, with optional voltage limiting means to ensure equal voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single semiconductor device is used in a conventional half-bridge circuit, then the circuit structure is simple, but the voltage blocking capability and on-resistance performance are limited
Solution Approach 1:
The patent divides a single semiconductor switch into multiple semiconductor switches connected in series (e.g., three switches per half-bridge leg). Each switch handles a portion of the total voltage, thereby increasing the overall voltage blocking capability while maintaining circuit functionality. This segmentation allows the circuit to operate at higher voltages without requiring a single high-voltage device with proportionally higher on-resistance.
2Reliability
If multiple semiconductor devices are connected in series to increase voltage blocking capability, then the voltage distribution becomes uneven, but this can be resolved with voltage limiting means
Solution Approach 1:
The patent incorporates voltage limiting means (such as zener diodes or avalanche diodes) connected in parallel with each semiconductor switch. These components provide automatic feedback control by clamping the voltage across each switch to a predetermined level. When voltage distribution becomes uneven, the voltage limiting means activates to redistribute the voltage, ensuring uniform voltage sharing across all series-connected switches without requiring complex external control circuits.
3Speed
If conventional semiconductor switches are used, then the switching speed is limited by high on-resistance, but the proposed configuration reduces on-resistance through parallel connection
Solution Approach 1:
The patent combines multiple semiconductor switches in a series-parallel configuration where switches are connected in series to achieve high voltage blocking capability, while their control terminals are connected in parallel to enable simultaneous switching. This merging approach allows all switches to operate together, effectively reducing the total on-resistance compared to a single switch, thereby decreasing switching losses and improving switching speed without compromising voltage handling capability.
Data Source
AI summary
A circuit has first and second semiconductor switches, each of which has a load path and control terminal connected in series. Each switch includes a first semiconductor device having a load path and a control terminal coupled to the control terminal of its switch, and a second semiconductor device having a load path between first and second load terminals, and a control terminal. Each second semiconductor device has its load path connected in series to the load path of the corresponding first semiconductor device. The semiconductor devices are coupled such that the second semiconductor devices are controlled by a load path voltage of the first semiconductor devices. The switches are integrated in a common semiconductor body. The first switch is implemented in a first area of the semiconductor body, and the second switch is implemented in a second area. In a horizontal plane, the first area surrounds the second area.