Halftone Mask Alignment for TFT Bridged Grain Lines
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Solution Overview
Problem
Existing manufacturing methods for thin film transistors in display devices face challenges in achieving uniformity and low leakage-current characteristics due to misalignment of bridged grain lines, which affects the reliability and performance of the devices.
Innovation Solution
A manufacturing method that uses a halftone mask with a reversely tapered photoresist to form a channel region with bridged grain lines, ensuring precise alignment and efficient removal of the photoresist without maximally influencing the gate pattern, thereby improving compatibility between the gate electrode and the bridged grain line in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional photoresist mask is used to form the channel region, then the gate pattern can be formed, but misalignment of bridged grain lines occurs affecting uniformity and leakage-current characteristics
Solution Approach 1:
The patent changes the physical parameters of the photoresist by creating a halftone mask with a reversely tapered profile. This involves controlling the photoresist thickness and exposure parameters to form a gradient structure where the photoresist thickness varies continuously, enabling precise alignment of bridged grain lines in the channel region while maintaining gate pattern integrity.
2Ease of manufacture
If the photoresist is completely removed to form the gate electrode, then the gate electrode can be formed, but the bridged grain lines may be damaged or misaligned
Solution Approach 1:
The patent applies preliminary action by forming the halftone mask with a reversely tapered profile before completing the gate electrode formation. This pre-formed gradient structure guides the subsequent etching and material deposition processes, ensuring that when the photoresist is removed, the bridged grain lines remain properly aligned and undamaged.
Solution Approach 2:
The halftone mask with reversely tapered profile acts as an intermediary structure between the gate pattern formation and the final gate electrode. This intermediate structure provides a controlled transition zone that protects the bridged grain lines during processing while enabling precise alignment, and is subsequently removed after serving its guiding function.
3Ease of manufacture
If the channel region is formed with wide intervals between grain lines, then manufacturing is easier, but device performance and uniformity deteriorate
Solution Approach 1:
The patent applies local quality by creating different photoresist thicknesses in different regions of the mask. The reversely tapered profile provides a gradient structure where the photoresist thickness varies locally, enabling precise control of grain line formation in the channel region while maintaining appropriate intervals for manufacturability. This local variation in photoresist properties achieves both ease of manufacture and device uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and performance of thin film transistors by maintaining uniformity and reducing leakage currents, ensuring consistent device characteristics and improved compatibility between the gate electrode and bridged grain lines.
Implementation Method 1
attaching a halftone mask formed using a photoresist onto the gate insulating layer
Implementation Method 2
forming a channel region including a plurality of bridged grain lines formed by doping impurities on the semiconductor layer
Implementation Method 3
exposing the gate insulating layer of the channel region by etching a part of the halftone mask
Implementation Method 4
removing the halftone mask may include removing the gate electrode layer from the gate insulating layer using a lift-off method of the halftone mask
Data Source
AI summary
A manufacturing method of a thin film transistor of a display device, the method including forming a gate insulating layer on a semiconductor layer; attaching a halftone mask onto the gate insulating layer; forming a channel region including a plurality of bridged grain lines formed; exposing the gate insulating layer of the channel region; forming a gate electrode layer on the halftone mask and the gate insulating layer; forming a gate electrode on the channel region by etching a portion corresponding to a boundary of the channel region of the gate electrode layer; removing the halftone mask; forming source/drain regions; forming an interlayer insulating layer on the gate electrode and the gate insulating layer; forming contact holes by etching the gate insulating layer and the interlayer insulating layer to expose the source/drain regions; and forming source/drain electrodes connected with the source/drain regions through the contact holes.