3D Hall Sensor Wafer Integration via Thermal Compression Bonding
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Solution Overview
Problem
Existing three-dimensional Hall sensor technologies face challenges in forming a spatially integrated Hall sensor structure with an integrated circuit on a wafer level plane, particularly in achieving reliable and warping-free connections between semiconductor wafers with different thermal expansion coefficients.
Innovation Solution
A component semiconductor structure is developed using a thermal compression joining method to integrate two semiconductor wafers with oxide layers, forming a shared insulating layer and a three-dimensional isotropic Hall sensor structure, with highly doped contact regions and a trench structure for precise magnetic field measurement, ensuring electrical connectivity and minimal warping due to identical semiconductor materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-contact holes are used to join ICs over a wide area, then electrical connectivity is achieved, but manufacturing complexity and warping increase
Solution Approach 1:
The invention extracts the connection function from through-contact holes spanning the entire wafer and concentrates it into localized contact areas. The sensor element is separated from the IC, with only necessary electrical connections maintained through minimal contact holes, eliminating the need for wide-area interconnections and reducing manufacturing complexity.
Solution Approach 2:
The wafer is segmented into distinct functional areas: the IC region and the sensor element region. This segmentation allows independent processing and connection strategies for each region, with the sensor element connected to the IC through a simplified interface rather than requiring comprehensive wafer-level interconnection.
2Adaptability or versatility
If semiconductor wafers with different thermal expansion coefficients are joined, then functional integration is achieved, but warping occurs
Solution Approach 1:
The invention applies local quality by creating an intermediate layer with specific thermal expansion properties at the interface between the first and second semiconductor wafers. This intermediate structure locally compensates for thermal expansion mismatches, allowing functional integration while maintaining overall wafer flatness and reducing warping.
3Measurement precision
If Hall sensor structure is integrated with IC on wafer level plane, then measurement precision is improved, but manufacturing difficulty increases
Solution Approach 1:
The sensor element and IC are processed separately on their respective wafers before final assembly. This preliminary action allows each component to be optimized independently using standard fabrication processes, and the thermal compression bonding step is performed as a final integration step, simplifying the overall manufacturing while achieving precise spatial magnetic field detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a spatially integrated three-dimensional Hall sensor with an integrated circuit on a wafer level plane, providing reliable and precise magnetic field measurements while minimizing warping and ensuring electrical operability between the Hall sensor and integrated circuit.
Implementation Method 1
The two oxide layers, i.e. the top surface of the first oxide layer and top surface of the second oxide layer, are integrally connected to each other by means of a thermal compression joining method
Implementation Method 2
at least three pairs of electrode pairs forming at least three four-contact structures, which each facilitate the measurement of a spatial component of the magnetic field, using the Hall effect
Data Source
AI summary
A component semiconductor structure having a semiconductor layer, which has a front side and a back side, at least one integrated circuit being formed on the front side and a first oxide layer being formed on the back side, a monolithically formed semiconductor body having a top surface and a back surface being provided, and a second oxide layer being formed on the back surface, and the two oxide layers being integrally connected to each other, and a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to the top surface, and at least three first highly doped semiconductor contact regions being formed on the top surface and at least three second highly doped semiconductor contact regions being formed on the lower surface.

