DRAM Hammer Refresh During Row Active Time
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Solution Overview
Problem
Conventional memory devices face performance degradation due to the collision between refresh operations and access operations, particularly in volatile memory devices like DRAM, where the refresh period is shortened as manufacturing scales down, leading to increased time loss and reduced system performance.
Innovation Solution
A memory device and system that perform a hammer refresh operation during the row active time of access operations, utilizing a refresh controller to control a row selection circuit, which activates a third wordline and concurrently performs a hammer refresh on an adjacent wordline identified by a mapping circuit, thereby reducing collision-induced time losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed separately from access operations, then memory cells are properly refreshed to prevent data loss, but system performance degrades due to collision between refresh and access operations
Solution Approach 1:
The patent merges the refresh operation with the access operation by performing the hammer refresh on the second wordline concurrently with the access operation on the third wordline. Both operations are executed within the same row active time period, eliminating the need for separate refresh timing and reducing collision between refresh and access operations.
Solution Approach 2:
The refresh operation continues without interruption by utilizing the row active time of access operations. Instead of pausing access operations to perform refresh, the system maintains continuous useful action by overlapping both operations in time, ensuring data retention while preserving system performance.
2Quantity of substance
If the refresh period is shortened to accommodate scaling down, then memory density increases, but time loss from refresh operations increases due to more frequent refresh requirements
Solution Approach 1:
The system performs hammer refresh operations periodically at predetermined intervals, but crucially overlaps these periodic refresh actions with regularly occurring access operations. This allows the refresh period to be shortened for higher density while the overlap mechanism prevents proportional increase in time loss.
Solution Approach 2:
The mapping circuit identifies the second wordline in advance as requiring hammer refresh before the actual refresh operation begins. This preliminary identification allows the refresh controller to prepare and execute the refresh concurrently with predicted access operations, reducing the impact of frequent refresh requirements on overall system time.
3Productivity
If a hammer refresh operation is performed on an adjacent wordline during access operation, then refresh efficiency improves by utilizing overlapping time, but device complexity increases due to mapping circuit and coordinated control
Solution Approach 1:
The row selection circuit is designed to be multi-functional, capable of selecting either the third wordline for access operations or the second wordline for hammer refresh operations, or both simultaneously. This universal circuit design consolidates multiple functions into a single component, improving refresh efficiency while minimizing the increase in device complexity.
Solution Approach 2:
The mapping circuit acts as an intermediary that receives the hammer address and determines the corresponding second wordline for refresh operations. This intermediary component simplifies the control logic by providing a direct mapping relationship, allowing the refresh controller to coordinate hammer refresh with access operations without requiring complex control circuits.
Data Source
AI summary
A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.