Hammer Refresh Row Address Detector for DRAM
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Solution Overview
Problem
Row hammer attacks pose a security threat to computing systems using DRAM by causing data loss in adjacent victim rows due to frequent access of aggressor rows, which existing DRAM devices struggle to mitigate effectively.
Innovation Solution
A hammer refresh row address detector is implemented, including a candidate aggressor row address count storage and a control logic unit that increments hit and miss counts, determines target aggressor rows, and generates victim row addresses for a hammer refresh operation, thereby anticipating and addressing potential row hammer attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DRAM device performs normal refresh operations every refresh period, then data stored in DRAM cells is maintained, but data in victim rows adjacent to frequently accessed aggressor rows is lost due to row hammer attacks
Solution Approach 1:
The patent performs hammer refresh operations on victim rows before data loss occurs by detecting frequent access patterns to aggressor rows. The control logic unit monitors access frequencies and triggers premature refresh of adjacent victim rows, preventing charge loss before it happens during normal operation.
Solution Approach 2:
The patent implements a feedback mechanism where the control logic unit continuously monitors row access patterns, compares them against threshold values, and dynamically adjusts refresh operations based on detected aggressor row behavior. This closed-loop system adapts refresh timing based on actual access patterns rather than following a fixed schedule.
2Reliability
If the DRAM device performs additional hammer refresh operations on victim rows, then data loss from row hammer attacks is prevented, but device complexity and operational overhead increase
Solution Approach 1:
The control logic unit serves multiple functions: it monitors row access patterns, identifies aggressor rows, determines victim rows, and triggers hammer refresh operations. By consolidating these functions into a single control unit rather than separate dedicated circuits, the patent reduces overall device complexity while maintaining comprehensive protection.
Solution Approach 2:
The system automatically detects and responds to row hammer attacks without external intervention. The control logic unit self-monitors access patterns and autonomously triggers refresh operations based on detected threats, eliminating the need for external control logic or manual configuration.
3Measurement precision
If the control logic unit monitors all row addresses to detect aggressor rows, then accurate detection of row hammer attacks is achieved, but processing time and operational overhead increase
Solution Approach 1:
Instead of uniformly monitoring all row addresses with equal intensity, the patent focuses monitoring resources on rows that exhibit suspicious access patterns. Once a potential aggressor row is detected through frequency comparison against threshold values, the system concentrates detection efforts on identifying its adjacent victim rows, rather than continuously analyzing the entire address space.
Solution Approach 2:
The patent performs partial monitoring by only fully analyzing rows that exceed the access frequency threshold. For rows below the threshold, the system performs minimal or no detailed analysis, reducing overall processing overhead while maintaining detection accuracy for actual aggressor rows.
Data Source
AI summary
A hammer refresh row address detector includes a control logic unit that receives a row address applied along with an active command, to increase a hit count stored in a corresponding entry when the row address is present in candidate aggressor row addresses stored in n entries. The control logic determines a candidate aggressor row address stored in an entry in which the hit count equals a threshold value to be a target aggressor row address. The control logic generates a victim row address adjacent to the target aggressor row address as a hammer refresh row address to accompany a hammer refresh command. The control logic increases the miss count value when the row address is not present in the candidate aggressor row addresses stored in the n entries and no hit count within the n entries is identical to the miss count value.