Hamming Code Check-Bit Layout for Narrower ECC Parity Circuits
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Solution Overview
Problem
Existing error correction code (ECC) implementations in data storage and communication require significant power consumption and circuit complexity due to the fixed number of redundant bits for parity and syndrome generation, limiting the reduction of parity bit-widths and increasing the complexity of error detection and correction.
Innovation Solution
The technique involves adding additional redundant check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix, reducing the parity bit-widths for check bit and syndrome generation without enhancing error correction capabilities, thereby reducing the number of XOR circuits and power requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If additional redundant check bits are added to increase the number of minimum weighted codes in the H-matrix, then the parity bit-width is reduced and circuit complexity is reduced, but the error correction capability is not enhanced
Solution Approach 1:
The patent changes the parameter of check bit allocation by adding redundant check bits specifically positioned to create more minimum weighted codes in the H-matrix. This parameter change reduces the parity bit-width required for syndrome generation while maintaining the same error correction capability, thereby reducing circuit complexity without enhancing correction capability.
Solution Approach 2:
The patent applies partial action by adding only the specific number of redundant check bits needed to achieve the desired reduction in parity bit-width, rather than adding excessive check bits that would enhance error correction capability. This targeted approach reduces circuit complexity while avoiding unnecessary increases in check bit quantity.
2Use of energy by moving object
If the number of check bits is increased to reduce parity bit-widths, then power consumption is reduced, but the number of redundant bits increases
Solution Approach 1:
The patent changes the parameter of check bit configuration by strategically adding redundant check bits to increase minimum weighted codes. This parameter change reduces the number of XOR circuits required for parity generation, thereby reducing power consumption while controlling the increase in redundant bits to only what is necessary for the optimization.
3Speed
If redundant check bits are added to increase minimum weighted codes, then operating speed is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameter of H-matrix structure by adding redundant check bits to create more minimum weighted codes. This parameter change reduces the parity bit-width, which reduces the number of XOR circuits and their interconnections, thereby improving operating speed while the increase in device complexity is offset by the reduction in parity circuit complexity.
Data Source
AI summary
A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.