Hamming Code Check-Bit Layout for Narrower Parity Generators
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Solution Overview
Problem
Existing error correction code (ECC) implementations in data storage and communication require a large number of redundant bits for parity and syndrome generation, leading to increased circuit complexity and power consumption, with limited reduction in parity bit-widths using additional check bits without improving error correction or detection capabilities.
Innovation Solution
The technique involves adding redundant check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix, specifically using extra check bits to reduce the width of the parity generating circuitry for check bit and syndrome generation without enhancing error correcting capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If additional redundant check bits are added to increase the number of minimum weight codes in the H-matrix, then the width of parity generators and XOR circuits is reduced, but the circuit complexity increases due to additional check bits
Solution Approach 1:
The patent changes the parameter of check bit allocation by adding redundant check bits specifically configured to increase the number of minimum weight codes in the H-matrix. This parameter change allows the system to reduce parity generator width while accepting increased check bit quantity, directly resolving the technical contradiction.
Solution Approach 2:
The patent applies excessive action by adding more check bits than the minimum required for basic error correction. These excessive check bits are strategically placed to increase minimum weight codes, which paradoxically reduces the overall circuit width by simplifying the XOR tree depth and reducing the number of XOR gates needed in parallel paths.
2Use of energy by moving object
If the number of check bits is increased to reduce parity bit-widths, then power consumption is reduced, but the number of XOR gates increases
Solution Approach 1:
The patent changes the structural parameter of the H-matrix by increasing minimum weight codes through redundant check bits. This parameter change reduces the depth of XOR trees, which directly reduces power consumption in clocked applications by shortening signal propagation paths, even though it may increase the total number of XOR gates.
Solution Approach 2:
The patent converts the potential harm of increased XOR gate count into a benefit by configuring these gates in a structure that reduces XOR tree depth. The additional gates are arranged to create shorter critical paths, which reduces dynamic power consumption and improves operating speed, transforming the disadvantage into an advantage for power-sensitive applications.
3Speed
If redundant check bits are added to increase minimum weighted codes, then operating speed is improved by reducing XOR tree depth, but circuit complexity increases
Solution Approach 1:
The patent changes the H-matrix configuration parameter to increase minimum weight codes, which directly reduces XOR tree depth. This parameter change improves operating speed by shortening the critical path for syndrome calculation, allowing faster error detection and correction in time-critical applications.
Solution Approach 2:
The patent performs preliminary action by pre-configuring the H-matrix with increased minimum weight codes before actual error correction operations. This preliminary structural arrangement ensures that XOR trees have reduced depth from the outset, enabling faster operation without requiring dynamic reconfiguration during runtime.
Data Source
AI summary
A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.