Hamming ECC Check-Bit Layout for Narrower Parity Generation
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Solution Overview
Problem
Existing error correction code (ECC) implementations in data storage and communication require significant power consumption and circuit complexity due to the fixed number of redundant bits for parity and syndrome generation, limiting the reduction of parity bit-widths and increasing the complexity of error detection and correction.
Innovation Solution
The technique involves adding additional redundant check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix, specifically using extra check bits to reduce the parity bit-widths for check bit and syndrome generation without enhancing error correction capabilities, thereby reducing the width of the parity generating circuitry and XOR gate count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of check bits is increased to reduce parity bit-widths, then circuit complexity and power consumption are reduced, but the number of redundant bits increases
Solution Approach 1:
The patent changes the parameter of check bit quantity from the minimum required for SEC/SED to an increased number that enables more Weight=2 codes in the H-matrix. This parameter change allows reduction of parity bit-widths while maintaining error correction capability, resolving the contradiction between circuit complexity and redundant bit quantity
Solution Approach 2:
The patent uses excessive check bits beyond the minimum required for error correction. This excessive action on check bit quantity enables the system to achieve lower parity bit-widths by increasing the number of Weight=2 codes, thereby reducing overall circuit complexity and power consumption
2Productivity
If the number of XOR gates is reduced to increase operating speed, then power consumption decreases, but circuit complexity increases
Solution Approach 1:
The patent changes the parameter of H-matrix structure by increasing Weight=2 codes through additional check bits. This parameter change reduces the number of XOR gates required for syndrome generation, thereby increasing operating speed while the increased check bit count compensates for the structural change
3Use of energy by moving object
If parity bit-widths are reduced to lower power consumption, then energy efficiency improves, but error detection capability may be compromised
Solution Approach 1:
The patent changes multiple parameters simultaneously: increases check bit quantity and increases Weight=2 codes in the H-matrix. This dual parameter change enables reduced parity bit-widths (lower power consumption) while maintaining sufficient error detection capability through the optimized H-matrix structure with more Weight=2 codes
Data Source
AI summary
A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.