Handle Substrate Isolation in Semiconductor Assemblies
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Solution Overview
Problem
Parasitic conduction in high voltage semiconductor devices limits their performance by allowing electrical current to flow even when the device is in an off state, due to the presence of a handle substrate that is not easily removable.
Innovation Solution
A method is introduced where a portion of an intermediary material, such as a sacrificial oxide, is removed between the semiconductor structure and the handle substrate, creating a gap for mechanical and electrical isolation. This allows the semiconductor structure to be decoupled from the handle substrate without additional complex processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a handle substrate is used to support the semiconductor structure during fabrication, then manufacturing ease is improved, but parasitic conduction increases due to electrical current leaking from the source-drain path
Solution Approach 1:
The patent segments the connection between the semiconductor structure and handle substrate by forming separate isolation regions. These isolation regions divide the continuous electrical path into isolated segments, preventing parasitic current flow while maintaining mechanical support through the handle substrate.
Solution Approach 2:
The patent extracts the electrical connection function from the mechanical support function. By removing or isolating the electrical pathway between the semiconductor structure and handle substrate while preserving the physical support, the patent eliminates parasitic conduction sources while maintaining manufacturing ease.
2Reliability
If the semiconductor structure is decoupled from the handle substrate to reduce parasitic conduction, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary isolation actions during the fabrication process itself, forming isolation regions and electrical connections before final device assembly. This preliminary decoupling of electrical paths simplifies subsequent manufacturing steps while achieving the desired parasitic conduction reduction.
Solution Approach 2:
The patent introduces intermediary structures such as isolation regions and intermediate electrical connections that mediate between the semiconductor structure and handle substrate. These intermediaries provide controlled electrical isolation while maintaining mechanical support, reducing manufacturing complexity compared to complete decoupling.
3Object-generated harmful factors
If isolation regions are formed to electrically isolate the semiconductor structure from the handle substrate, then parasitic conduction is reduced, but manufacturing steps increase
Solution Approach 1:
The patent merges the formation of isolation regions with existing fabrication processes such as epitaxial growth or selective etching. By combining multiple functions into single process steps, the patent reduces the total number of manufacturing steps while achieving effective electrical isolation.
Solution Approach 2:
The patent designs isolation regions and intermediary structures that serve multiple functions simultaneously: providing electrical isolation, maintaining mechanical support, and facilitating subsequent processing steps. This multi-functionality reduces the overall manufacturing complexity despite adding isolation features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic conduction by isolating the semiconductor structure from the handle substrate, thereby enhancing the operational performance and manufacturing efficiency of high voltage semiconductor devices.
Implementation Method 1
A method is introduced where a portion of an intermediary material, such as a sacrificial oxide, is removed between the semiconductor structure and the handle substrate
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~2
AI summary
Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.