Capacitors in Handle Wafer Cavities for IC Package Integration
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Solution Overview
Problem
The thinness of interposer wafers in integrated circuit packages limits the vertical height and surface area of discrete electrical components like capacitors, restricting their capacitance and functionality.
Innovation Solution
Fabricating discrete electrical components, such as capacitors, within the handle wafer's cavities, which allows for efficient use of volume and increased capacitance by forming electroconductive layers and structures that extend beyond the wafer's surface, enabling a stacked alignment with interposer capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interposer wafer is made substantially thin to reduce package size, then the vertical height of discrete electrical components is limited, but the capacitance and functionality of these components are reduced
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional vertical capacitor structures by forming cavities in the handle wafer and building capacitors that extend vertically into these cavities. This dimensional change allows capacitors to achieve greater effective surface area and capacitance within the constrained vertical space of thin interposer wafers, resolving the contradiction between reduced package size and maintained capacitance.
Solution Approach 2:
The patent embeds discrete electrical components, particularly capacitors, within cavities formed in the handle wafer structure. These components are nested within the existing wafer architecture, allowing them to occupy space that would otherwise be unused, thereby maintaining component functionality while preserving the thin-profile advantage of the interposer wafer design.
2Area of stationary object
If discrete electrical components are formed on the surface of the interposer wafer, then they are accessible for connection, but the available surface area is limited due to the thin wafer structure
Solution Approach 1:
The patent segments the handle wafer by forming cavities that create distinct regions for housing discrete electrical components. This segmentation allows components to be positioned in dedicated spaces within the wafer thickness, providing both adequate surface area for component formation and structured access points for electrical connections without compromising wafer integrity.
Solution Approach 2:
The patent introduces electroconductive pads and vias as intermediary structures that facilitate electrical connections between the vertically extended capacitor structures and the external circuitry. These intermediaries bridge the gap between the three-dimensional component structures and the two-dimensional connection interfaces, maintaining ease of operation despite the vertical component architecture.
Data Source
AI summary
Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.