Handle Wafer Diode Integration via Isolation Layer
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Solution Overview
Problem
Existing integrated circuit designs face challenges in efficiently forming large diodes on handle wafers without increasing the active surface area, while maintaining isolation from other semiconductor devices and preventing latch-up or interference.
Innovation Solution
The integration of a handle wafer with multiple doped regions and a bonded oxide isolation layer allows for the formation of large diodes, such as zener and clamping diodes, in the handle wafer, which are electrically isolated from circuit wafer devices, using silicon on insulator technology and via connections for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large diodes are formed on handle wafers, then ESD/Surge tolerance is improved, but active surface area increases
Solution Approach 1:
The patent forms large diodes in the handle wafer substrate rather than on the active circuit wafer surface. By utilizing the vertical dimension and the handle wafer's bulk material, large-area diodes can be created without consuming additional active surface area on the circuit wafer, thus resolving the contradiction between ESD tolerance and surface area usage.
Solution Approach 2:
The patent separates the ESD protection function from the active circuitry by placing diodes in the handle wafer layer. This segmentation allows the ESD protection structure to be formed independently in the handle wafer without interfering with the active circuit elements on the circuit wafer, enabling large diode formation without increasing active surface area.
2Reliability
If diodes are formed in handle wafer, then isolation from circuit wafer devices is improved, but device complexity increases
Solution Approach 1:
The patent introduces an isolation layer as an intermediary between the handle wafer and the circuit wafer. This isolation layer provides electrical separation, allowing diodes to be formed in the handle wafer with guaranteed isolation from circuit wafer devices. The via structure acts as a controlled intermediary connection point, simplifying the overall isolation strategy while maintaining reliability.
3Productivity
If via connections are used for electrical connections, then connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms vias through the isolation layer as a preliminary step before completing the electrical connection process. By pre-establishing the via pathways through the isolation layer, the subsequent metallization and connection steps are simplified, improving overall connection efficiency while managing manufacturing complexity through staged processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of diodes that can handle ESD/Surge tolerances without affecting other circuitry, maintaining low capacitance and preventing latch-up, while allowing for compact integration and efficient electrical connections.
Implementation Method 1
a bonded oxide isolation layer allows for the formation of large diodes, such as zener and clamping diodes, in the handle wafer, which are electrically isolated from circuit wafer devices
Data Source
AI summary
A method for through active-silicon via integration is provided. The method comprises forming an electrical device in a handle wafer. The method also comprises forming an isolation layer over the handle wafer and the electrical device and joining an active layer to the isolation layer. Further, the method comprises forming at least one trench through the active layer and the isolation layer to expose a portion of the handle wafer and depositing an electrically conductive material in the at least one trench, the electrically conductive material providing an electrical connection to the electrical device through the active layer.