Handshake-Free Multi-Processor Memory Access Architecture
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Solution Overview
Problem
Existing memory access protocols for multi-processor systems are complex and inefficient, particularly when multiple processors need to share a single memory unit, as they require handshakes and error detection/correction mechanisms, making them unsuitable for intermittent access scenarios.
Innovation Solution
A processor architecture where a first processor, with more processing power, controls access to a shared memory unit using a handshake-free protocol, allowing a second processor to access the memory by sending an interrupt request and taking control upon acknowledgement, with the first processor remaining idle during this time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a handshake protocol is used for multi-processor memory access, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error detection and correction provisions from the memory access protocol, retaining only the essential hand-shake mechanism for memory access control. This removes unnecessary complexity while preserving reliability for the specific use case of intermittent multi-processor access.
Solution Approach 2:
Instead of using a complex protocol with built-in error detection and correction, the patent inverts the approach by using a simple hand-shake protocol without these provisions, relying on the nature of the application (intermittent access) to make error handling unnecessary.
2Speed
If separate memory units are provided for each processor, then access speed is improved, but loss of substance increases
Solution Approach 1:
The patent merges multiple memory units into a single shared memory resource that can be accessed by multiple processors. The hand-shake protocol coordinates access to this shared resource, eliminating the need for separate memory units while maintaining efficient access through proper arbitration.
Solution Approach 2:
The single memory unit is designed to serve multiple processors universally, rather than being dedicated to a single processor. The hand-shake mechanism enables this memory unit to function for multiple masters, improving resource utilization while maintaining access performance.
3Adaptability or versatility
If format translation is implemented, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent makes both processors support the same simple hand-shake protocol, eliminating the need for format translation. This homogeneous approach to protocol support simplifies the system while maintaining adaptability, as both processors can directly communicate with the shared memory using the same mechanism.
4Reliability
If handshake protocol is used, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent applies a partial hand-shake mechanism that provides essential reliability without the full overhead of complete error detection and correction. The hand-shake ensures proper coordination for intermittent access while minimizing the time processors spend in non-productive states.
Data Source
AI summary
A system arrangement including a memory unit having a memory interface in accordance with a handshake-free protocol between the memory and an accessing master, a bus connected to the memory unit and first and second masters. The first master operative to access the memory unit through the bus and the memory interface and operative to perform interrupts following reception of an interrupt request through an interrupt interface. The second master operative to access the memory unit through the bus and memory interface. The second master being configured to transfer an interrupt request to the first processor before accessing the memory unit.