Handshake Logic Circuits for Clock-Skew-Free IC Interconnects
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Solution Overview
Problem
Designing reliable clock networks for large programmable integrated circuits (ICs) is challenging due to clock skew issues, which require significant engineering resources and can impact the design cycle, and the extensive global clock networks consume substantial power.
Innovation Solution
The integration of novel handshake circuits, including a ready multiplexer, acknowledge demultiplexer, C-element, logic gate, and storage elements, which enable asynchronous routing and reduce the need for large global clock networks by using pipelined interconnect structures and handshake logic to manage data transfer efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extensive dedicated clock networks with clock management blocks (DLLs, PLLs, DCMs) are used to provide global clock signals to all portions of the IC, then clock distribution coverage is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent removes the extensive dedicated clock network and clock management blocks from the system. Instead of using global clock signals distributed through DLLs, PLLs, and DCMs, the invention extracts only the essential timing function and implements it locally at each logic block using handshake logic and storage elements, thereby eliminating the power-consuming global clock distribution infrastructure while maintaining clock distribution coverage
Solution Approach 2:
The patent segments the monolithic clock distribution system into independent local timing units at each logic block. Each logic block contains its own storage elements and handshake logic that independently manage timing without relying on a centralized clock network, thus reducing overall power consumption while maintaining adaptability across the IC
2Reliability
If extensive dedicated clock networks with multiple DCMs are used to provide individual clock deskewing, frequency synthesis, phase shifting, and dynamic reconfiguration, then clock signal quality and functionality are improved, but device complexity and design time increase
Solution Approach 1:
The patent implements self-service timing management where each logic block contains its own storage elements and handshake logic that automatically manage local timing requirements. This eliminates the need for complex centralized clock management blocks while maintaining reliable timing through distributed, autonomous timing units that adapt to local needs without requiring global clock synchronization
Solution Approach 2:
Instead of using a centralized clock network to impose timing on logic blocks, the patent inverts the approach by having each logic block generate its own timing signals through local storage elements and handshake logic. This inversion eliminates the complexity of global clock distribution while maintaining timing reliability through bottom-up timing management
3Adaptability or versatility
If global clock networks are used to provide clock signals at virtually any position in the programmable IC, then clock accessibility is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by providing timing functionality locally at each logic block through storage elements and handshake logic, rather than distributing clock signals globally. Each logic block has its own timing resources that are activated only when needed, eliminating the need for power-consuming global clock networks while maintaining clock accessibility throughout the IC
Data Source
AI summary
Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a first input coupled to a control output of the C-element, and a second input. The storage element includes a data multiplexer and a latch. The data multiplexer has M data inputs coupled to data inputs of the storage element, a select input coupled to the output of the logic gate, and a data output, M being an integer greater than one. The latch has a data input coupled to the data output of the first data multiplexer and an output coupled to an output of the storage element. The logic gate can be a logical AND gate with the second input coupled to a memory cell.