Handshake Watchdog Timer for Power Management IC Fault Detection
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Solution Overview
Problem
Existing processing systems face challenges in efficiently managing power transitions, particularly in safety-critical applications, due to miscommunication between processors and power management ICs, leading to unexpected power downs and increased power consumption.
Innovation Solution
The implementation of a handshake watchdog (HWD) timer in the power management circuitry, which sets a maximum delay time for the transition from an initial wakeup request to a qualified wakeup request, allowing for timely fault detection and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a periodic watchdog (PWD) timer is used to prevent the processor from becoming stuck in standby mode, then the processor can be periodically restarted to service the timer, but this forces wakeups even when not needed, consuming unnecessary energy and causing significant delay in detecting faults in the wakeup mechanism
Solution Approach 1:
The patent implements a feedback mechanism where the processor monitors its own wakeup status and sends acknowledgment signals to the PMIC. The PMIC's handshake watchdog timer is triggered only when needed (upon receiving a wakeup request from the processor), and the processor provides feedback by sending a qualified wakeup request to clear the timer. This eliminates the need for periodic forced wakeups while maintaining reliable fault detection through the conditional handshake mechanism.
Solution Approach 2:
The processor services the watchdog timer itself by monitoring its own wakeup status and sending the qualified wakeup request to clear the PMIC's timer when the wakeup is complete. This self-service approach eliminates the need for external periodic forcing of wakeups, allowing the system to remain in low-power mode until actually needed, thereby reducing unnecessary power consumption while maintaining reliability.
2Use of energy by moving object
If the processor stays in low power mode indefinitely due to broken communication or processor level fault, then power consumption is minimized, but the system becomes unresponsive and unable to transition to a safe state
Solution Approach 1:
The patent establishes a preliminary handshake agreement between the processor and PMIC before the processor enters low-power mode. The PMIC's handshake watchdog timer is pre-configured with a maximum delay time, and the processor is required to send a qualified wakeup request within this timeframe to clear the timer. This preliminary arrangement ensures that if the processor fails to respond (indicating a fault), the timer will expire and trigger a reset, preventing the system from staying unresponsive indefinitely while still allowing normal low-power operation.
Solution Approach 2:
The handshake watchdog timer acts as a cushion or safety mechanism that is prepared in advance. It provides a time window for the processor to complete its wakeup sequence and send the qualified wakeup request. If the processor fails due to a fault, the timer expires and triggers a reset, preventing the system from remaining stuck in low-power mode. This beforehand cushioning allows the system to safely tolerate minor delays while protecting against catastrophic failures.
3Use of energy by moving object
If the PMIC removes power at an incorrect time due to miscommunication with the processor, then power consumption is reduced, but the processor and peripherals are unexpectedly powered down, causing safety issues in critical applications
Solution Approach 1:
The patent implements a two-way feedback handshake mechanism where the processor not only receives power control signals from the PMIC but also sends acknowledgment signals back. The processor sends an initial wakeup request to the PMIC, and upon completing its wakeup sequence, sends a qualified wakeup request back to the PMIC to confirm successful transition. This bidirectional feedback ensures that the PMIC only removes or restores power when the processor is in the correct state, preventing unexpected power downs while still enabling power savings during actual low-power periods.
Solution Approach 2:
The handshake watchdog timer acts as an intermediary mechanism between the processor and PMIC power control logic. It mediates the power transition by providing a time window for the processor to complete its wakeup sequence before the PMIC is allowed to remove power. The timer ensures that power transitions only occur after the processor has had sufficient time to respond and complete its state changes, preventing premature power removal while still enabling power management functionality.
Data Source
AI summary
Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.