Self-Aligned Backside Gate Contacts Using HAR Features
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Solution Overview
Problem
The increasing functional density of semiconductor devices, particularly in three-dimensional structures, leads to front side wiring congestion and parasitic gate capacitance issues, necessitating innovative solutions to manage power delivery and device interconnections.
Innovation Solution
The implementation of self-aligned backside gate connections through high aspect ratio features, allowing for local wiring of the gate from the backside of the device substrate, reducing front side wiring congestion and parasitic gate capacitance by moving gate local wiring to the less congested backside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If functional density is increased in three-dimensional structures, then device capacity and integration are improved, but front side wiring congestion and parasitic gate capacitance increase
Solution Approach 1:
The patent moves gate wiring from the front side (two-dimensional plane) to the back side of the substrate, utilizing the third dimension (depth/vertical space) to resolve wiring congestion. By forming HAR features that extend through the substrate thickness, gate connections are established on the less congested backside, effectively adding a spatial dimension to the wiring architecture.
Solution Approach 2:
The substrate wiring is segmented into front-side and back-side connections. The front side handles source/drain and interconnect wiring, while the back side is dedicated to gate wiring. This segmentation separates conflicting wiring functions into distinct spatial zones, reducing parasitic capacitance and congestion on the front side.
2Ease of operation
If front side wiring is used for gate connections, then device interconnection is achieved, but parasitic gate capacitance increases
Solution Approach 1:
Gate connections are relocated from the front-side plane to the back-side of the substrate through HAR features. This vertical transition reduces the overlapping area between gate wiring and other conductive elements, thereby minimizing parasitic capacitance while maintaining effective gate interconnection.
Solution Approach 2:
The gate wiring function is extracted from the congested front-side wiring layer and relocated to the back side. This separation removes the harmful parasitic capacitance effect by physically distancing the gate connection path from other front-side conductors.
3Adaptability or versatility
If HAR features are formed through the substrate, then backside gate wiring is enabled, but manufacturing process complexity increases
Solution Approach 1:
The HAR features are formed early in the fabrication process, before final device assembly, using self-aligned etching techniques. The mandrel structures are pre-formed to guide the HAR feature formation, ensuring precise alignment without requiring complex post-processing steps.
Solution Approach 2:
The self-aligned etching process uses the mandrel structures themselves as alignment references, eliminating the need for separate alignment markings or complex photolithography steps. The process is self-correcting, where the mandrel geometry automatically defines the HAR feature position and dimensions.
Data Source
AI summary
Embodiments of the present disclosure relate to a method of forming a contact structure on a substrate. The method includes forming a high aspect ratio (HAR) feature within a substrate having a device formed thereon. The device includes a plurality of channels disposed through a polysilicon layer and extending in a first direction, and an isolation layer disposed on the substrate, the polysilicon layer separated from the isolation layer by a dielectric layer. The forming of the HAR feature is formed a first distance in a second direction from the plurality of channels and includes removing a portion of the isolation layer and the polysilicon layer. The method further includes etching the polysilicon layer to expose a top surface of the isolation layer that is opposite to a surface that is disposed on the surface of the substrate, and exposing a metal layer within the HAR feature.