High Aspect Ratio Silicon Core Capacitors for DC/DC Miniaturization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current silicon interposer structures for high-density stacked applications, such as in smartphones and medical devices, face challenges in achieving high capacitance density due to limitations in the interdigitated comb type capacitors, which do not adequately address the miniaturization requirements for DC/DC converter modules.
Innovation Solution
The development of high aspect ratio conductor-dielectric-silicon (CDS) structures using a modified HARMS process, which increases capacitance per unit area by creating textured surfaces with high aspect ratio silicon cores and dielectric layers, allowing for capacitance densities of 8-150 nF/mm² with a 10V breakdown voltage, surpassing standard MOS capacitor values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If interdigitated comb type capacitors are used in silicon interposer structures, then high packing density and high Q inductors are achieved, but capacitance density is insufficient for DC/DC converter module miniaturization
Solution Approach 1:
The patent transitions from planar interdigitated comb type capacitors to three-dimensional high aspect ratio CDS structures. By etching deep trenches (50-200 micrometers) into the silicon interposer and filling them with conductive material, the capacitor surfaces extend vertically into the third dimension, dramatically increasing capacitance density from typical planar values to 8-150 nF/mm²
Solution Approach 2:
The patent creates a textured surface structure with high aspect ratio silicon cores surrounded by dielectric material and conductive layers. This porous-like three-dimensional architecture with vertical walls and internal surfaces provides vastly increased surface area within the same footprint, enabling capacitance densities 25-50 times higher than standard MOS capacitors
2Quantity of substance
If standard MOS capacitor structures are used, then simple fabrication is maintained, but capacitance density remains too low for high-performance PMIC applications
Solution Approach 1:
The patent divides the capacitor structure into discrete high aspect ratio segments or trenches etched into the silicon interposer. Each trench is filled with conductive material and surrounded by dielectric, creating modular repeating units that can be densely packed. This segmentation enables the complex three-dimensional structure to be fabricated using standard trench etching and filling processes
Solution Approach 2:
The patent creates a composite structure combining silicon cores, dielectric materials (such as silicon dioxide), and conductive materials (such as copper or aluminum). This multi-material composite approach within the CDS structure leverages the advantageous properties of each material to achieve high capacitance density while maintaining compatibility with existing semiconductor fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in capacitance densities 25-50 times higher than standard MOS capacitors with the same breakdown voltage, enabling suitable applications in power management integrated circuits and providing tunable capacitance for RFIC and VCO applications.
Implementation Method 1
capacitance densities of 8-150 nF/mm² with a 10V breakdown voltage
Implementation Method 2
an electrical conductor layer overlying the Si core, forming a conductor-silicon (CS) structure. In the case of a capacitor, the high aspect ratio structure further includes a dielectric layer interposed between the Si core and electrical conductor
Data Source
AI summary
High aspect ratio passive electrical components are presented formed from a single-piece silicon (Si) substrate having a textured surface with at least one high aspect ratio structure. The high aspect ratio structure includes a Si core having a width (CX), a height (CZ), and a minimum aspect ratio of CZ-to-CX of at least 5:1. An electrical conductor layer overlies the Si core. The electrical component may be a capacitor, inductor, or transmission line. In the case of a capacitor, the substrate textured first surface is made up of a plurality of adjacent high aspect ratio conductor-dielectric-Si (CDS) structures. Each CDS structure includes: a Si core, a dielectric layer overlying the Si core, and an electrical conductor layer overlying the dielectric layer. The Si cores may be formed in the geometry of parallel ridges, columns, or as a honeycomb. Each Si core comprises at least 90% of the CDS structure height.