Hard Decoder Using Extrinsic Bit Reliability for Flash Memory
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Solution Overview
Problem
Flash memory devices, such as NAND flash memory, experience errors due to noise and interference during programming and read operations, leading to inaccuracies in stored information bits, which existing error correction codes struggle to address efficiently without increasing complexity or latency.
Innovation Solution
A hard decoder system that utilizes extrinsic page information from neighboring bits to determine the reliability of bits in a page, allowing for targeted error correction decisions without additional latency, thereby enhancing error correction capability and reducing system latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes are used to correct errors in flash memory devices, then error correction capability is provided, but latency increases and complexity increases
Solution Approach 1:
The patent segments the error correction process by dividing bits into reliable and unreliable categories based on extrinsic information. The decoder only performs correction operations on unreliable bits rather than all bits, segmenting the work to reduce latency while maintaining error correction capability for the most problematic bits.
Solution Approach 2:
The patent applies local quality by treating different bits differently based on their reliability characteristics. Extrinsic information from neighboring bits is used to locally assess reliability, and correction is applied selectively only where needed (unreliable bits) rather than uniformly across all bits, reducing overall processing latency.
2Reliability
If strong error correction codes are used to allow fast programming and reads under high stress conditions, then error correction capability improves, but digital signal processing complexity increases
Solution Approach 1:
The patent extracts and utilizes extrinsic information from neighboring bits as an additional error correction resource. This external information source is taken out from the traditional ECC framework and integrated into the decoding process, enabling the system to handle higher stress conditions without requiring more complex conventional ECC algorithms.
Solution Approach 2:
The patent performs preliminary assessment of bit reliability using extrinsic information before the main error correction process. By pre-identifying unreliable bits through neighborhood analysis, the system prepares a targeted correction list that simplifies the subsequent correction operations, reducing overall DSP complexity.
3Reliability
If extrinsic page information is obtained by additional NAND reads, then error correction capability improves, but latency increases
Solution Approach 1:
The patent merges the extrinsic information gathering process with the existing read operation. Instead of performing separate reads to obtain neighborhood bit information, the system combines this data collection with the primary read operation, utilizing available read bandwidth efficiently and avoiding additional latency-inducing read cycles.
Data Source
AI summary
Aspects can include selecting memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second plurality of pages including corresponding second pluralities of bits, obtaining, based on the second pluralities of bits, extrinsic page information for a proposed error solution including a third plurality of bits indicating a reliability of respective bits of the first plurality of bits, and rejecting, in response to a determination that the proposed error solution indicates a modification to a reliable bit among the first plurality of bits, the proposed error solution to eliminate a false correction of the first plurality of bits.