Hard-Input FEC Receiver with Bit-Specific LLR Demapping

Solution Overview

Problem

Existing digital receivers for FEC-encoded data in PON systems face performance degradation due to complex symbol demapping and decoding processes, particularly in multi-rate PON systems using modulation formats like PAM4 and PAM3, which require advanced and costly circuitry for accurate error correction.

Innovation Solution

A digital receiver employing a one-dimensional hard-input demapper with an LLR generator that assigns specific LLR magnitudes based on the probability of error in demapped bits, improving performance without increasing component complexity, and applicable to various communication channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If soft-input LDPC decoding with ADC is used to achieve optimal performance, then receiver performance is improved, but device complexity and cost increase significantly

Engineering Contradiction:

Improvereceiver performanceVSAvoidcircuitry complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces expensive, complex soft-input decoding circuitry with a simpler hard-input demapper followed by an LLR generator. The hard demapper produces coarse decisions that are then refined by generating LLRs with magnitudes scaled according to bit reliability information, achieving near-optimal performance with much lower complexity and cost.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the parameter representation by generating LLRs with magnitudes that are scaled based on bit reliability information from the hard demapper. This parameter adjustment allows the system to convey reliability information without requiring the full complexity of soft-input decoding, effectively trading detailed soft information for a simpler structure with adaptively scaled LLRs.

Inventive Principle:

Principle #35Parameter changes

2Device complexity

If hard-input demapper is used to reduce complexity, then device complexity is reduced, but measurement precision of bit reliability information deteriorates

Engineering Contradiction:

Improvecircuitry complexityVSAvoidbit reliability information accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent introduces an LLR generator as an intermediary component between the hard demapper and the LDPC decoder. This intermediary takes the hard decisions from the demapper and generates LLRs with magnitudes that are scaled according to bit reliability information, thereby recovering reliability information that would otherwise be lost in the hard decision process.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter representation by generating LLRs with magnitudes that are scaled based on bit reliability information from the hard demapper. This parameter adjustment allows the system to convey reliability information without requiring the full complexity of soft-input decoding, effectively trading detailed soft information for a simpler structure with adaptively scaled LLRs.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentEP4304096B1One-dimensional hard-input FEC receiver for digital communication

Publication Date: 2025.03.26 NOKIA SOLUTIONS & NETWORKS OY

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Figure 3(a)~3(c)
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AI summary

A digital receiver based on one-dimensional hard demapping of an input symbol stream (FEC encoded) is configured to utilize LLRs created to have bit-specific magnitude values to improve the probability that the included decoder (such as an LDPC decoder) properly recovers each bit from the original stream. The digital receiver may be used with various types of data modulation schemes (e.g., PAM3, PAM4, DSQ8, etc.), with a specific set of LLR magnitudes created for each modulation scheme.