Hard-Limiter Demodulation With Digital Frequency Offset Compensation
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Solution Overview
Problem
Conventional demodulators for MPSK and DMPSK signals face challenges such as high power consumption due to analogue-to-digital conversion, complex circuit configurations requiring VCO or NCO, and sensitivity to non-linearity in RF components, leading to performance degradation, especially for strong input signals.
Innovation Solution
The proposed apparatus and method utilize a hard limiter stage to convert analogue signals to two-level signals, followed by a digital down converter and low pass filter to generate baseband signals, with stages for symbol synchronization, instantaneous phase detection, differential detection, frequency offset compensation, and demapping to produce demodulated outputs, reducing the need for complex analogue-to-digital conversion and improving robustness against non-linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If analogue-to-digital conversion is used in traditional demodulators, then signal processing capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent replaces the analogue-to-digital converter (ADC) with a hard limiter circuit that directly processes analogue signals. Instead of converting the signal to digital form for processing, the system uses a hard limiter to clip the signal amplitude to two levels, eliminating the need for power-consuming ADC hardware while maintaining signal processing capability through subsequent digital signal processing stages.
Solution Approach 2:
The patent employs a hard limiter circuit as a simple, low-cost alternative to the expensive and power-intensive ADC. The hard limiter uses basic electronic components (comparators, resistors, capacitors) that consume minimal power compared to the ADC, providing a cost-effective solution for signal thresholding and processing.
2Measurement precision
If VCO or NCO is used for carrier phase and frequency tracking, then frequency offset compensation is improved, but circuit complexity increases
Solution Approach 1:
The patent replaces the analogue VCO/NCO frequency tracking mechanism with a digital frequency offset estimation and compensation system. The system uses digital signal processing techniques to estimate frequency offset and apply correction through digital mixers and phase rotators, eliminating the need for complex analogue VCO/NCO circuits while maintaining frequency compensation capability.
Solution Approach 2:
Instead of using a VCO to generate a tracking carrier signal, the patent creates a digital copy of the frequency offset characteristics through signal processing. The system estimates the frequency offset from the received signal and generates corrective phase and frequency adjustments through digital operations, effectively copying the frequency tracking function without requiring physical VCO/NCO hardware.
3Use of energy by moving object
If hard limiter is used to replace analogue-to-digital conversion, then power consumption is reduced, but performance degradation occurs due to non-linearity sensitivity
Solution Approach 1:
The patent implements feedback mechanisms through frequency offset estimation and compensation stages that continuously monitor and correct signal distortions. The system estimates frequency offset from the hard-limited signal and applies corrective phase rotations and frequency adjustments to compensate for non-linearity effects, thereby maintaining demodulation performance while using the power-efficient hard limiter approach.
Solution Approach 2:
The patent compensates for non-linearity by dynamically adjusting frequency and phase parameters through digital signal processing. The system changes the frequency offset and phase rotation parameters based on the received signal characteristics, allowing the hard-limited signal to be properly demodulated despite the non-linearity introduced by the hard limiter, thus maintaining reliability while reducing power consumption.
Data Source
AI summary
An apparatus for demodulating an analogue input signal comprises a hard limiter stage (4) for converting the signal to a two level signal. A digital down converter/low pass filter stage (6) converts the signal to a base band signal, and a symbol synchronization stage (8) extracts symbol timing. An instantaneous phase detector (10) calculates the instantaneous phase of the one or more symbols associated with the input signal. If the input signal has been modulated according to a pi/4DQPSK, pi/2DBPSK, GMSK, or a GFSK modulation scheme, a differential detector (12) determines a difference in the phase between adjacent symbols, a coarse frequency offset compensation stage (14) applies a compensation signal to compensate for frequency offset, and a frequency offset estimation stage (16) updates this compensation signal. A demapper (18) generates a demodulated output signal after compensation by the frequency offset compensation stage.