Hard Mask Removal by CMP for Uniform Gate Stack Planarity
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Solution Overview
Problem
The challenge in IC fabrication is efficiently removing a hard mask deposited over a polysilicon layer without causing uneven etch rates due to varying pattern densities in isolated and dense regions, which can lead to non-planar surfaces and material loss.
Innovation Solution
A method involving chemical mechanical polishing (CMP) and flowable chemical vapor deposition (FCVD) is used to deposit and planarize a dielectric layer, ensuring uniform removal of the hard mask and dielectric layer across different regions, maintaining a planar surface without the need for photolithography or additional etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to remove hard mask, then the hard mask can be removed, but uneven etch rates occur due to varying pattern densities in isolated and dense regions leading to non-planar surfaces and material loss
Solution Approach 1:
A dielectric layer is deposited as an intermediary material over the hard mask layer. This dielectric layer serves as a mediator that enables uniform removal of the underlying hard mask through CMP processing. The dielectric layer is specifically engineered to have different removal rates relative to the hard mask, allowing the CMP process to selectively remove the dielectric while exposing and subsequently removing the hard mask in a controlled manner, achieving uniform removal across isolated and dense regions without the uneven etching problems of conventional methods
Solution Approach 2:
The patent replaces the chemical etching process with a mechanical-polishing process (CMP). Instead of using chemical reactions that exhibit loading effects and uneven removal rates based on pattern density, the invention employs mechanical polishing to remove the dielectric layer and underlying hard mask. This mechanical substitution eliminates the harmful loading effects inherent in chemical etching, achieving uniform material removal across the wafer surface regardless of local pattern density variations
2Manufacturing precision
If CMP is used to planarize the dielectric layer, then a planar surface is achieved, but additional process steps are required compared to conventional etching
Solution Approach 1:
The patent merges multiple functions into the CMP process step. The CMP operation simultaneously performs: (1) planarization of the dielectric layer surface, (2) selective removal of the dielectric layer to expose the hard mask, and (3) subsequent removal of the hard mask itself. By combining these normally separate functions into a single integrated CMP process, the invention achieves high planarity while actually reducing the total number of process steps compared to conventional approaches that would require separate etching and planarization steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves uniform material removal across varying pattern densities, preserving a planar structure and minimizing material loss, thereby enhancing the fabrication process efficiency and quality of integrated circuits.
Implementation Method 1
A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
Implementation Method 2
A dielectric layer is deposited on the substrate and on the patterned gate stacks using a flowable chemical vapor deposition (FCVD) process
Data Source
AI summary
A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.