Hard Mask Patterning for Source/Drain Contact Margin Control
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Solution Overview
Problem
Current semiconductor device manufacturing processes face challenges in achieving high design flexibility and reliability for local interconnects, particularly in connecting source/drain regions to metal wiring layers, due to limitations in patterning techniques and material deposition methods.
Innovation Solution
The process involves forming a source/drain contact layer on the semiconductor device, using directional patterning techniques such as ion implantation or etching to adjust the width of photo resist patterns, allowing for precise formation of source/drain contact layers that enhance connectivity and reduce device size, while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning techniques are used for source/drain contact layers, then manufacturing process is simpler, but manufacturing precision and design flexibility are insufficient
Solution Approach 1:
The patterning process is divided into multiple sequential steps: forming mandrels with first pitch, depositing spacers, selectively removing portions, and repeating the process to achieve final patterns with smaller pitch. This segmentation enables precise control of contact layer dimensions while managing complexity through systematic process breakdown
Solution Approach 2:
Mandrels are formed in advance as templates before the actual contact layer patterning. These preliminary structures guide subsequent spacer deposition and material filling, ensuring precise positioning and dimensions are achieved before final contact layer formation
2Adaptability or versatility
If local interconnect structures are added to enhance connectivity, then design flexibility improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The same segmented patterning process is used to form both standard contact layers and local interconnect structures. The methodology universally applies to different interconnect configurations (straight, bent, extended) by simply modifying the mandrel and spacer placement patterns, enabling design flexibility without requiring separate manufacturing processes
Solution Approach 2:
Local interconnect structures are formed by extending contact layers in specific directions using directional spacer deposition and selective removal. This approach adds spatial dimensionality to standard contacts, creating bent or extended paths that provide design flexibility for routing while using the same fundamental patterning techniques
3Reliability
If photo resist pattern width is not adjusted, then manufacturing process is faster, but deformation issues occur and reliability decreases
Solution Approach 1:
Physical adjustment of photo resist pattern width through controlled deformation is replaced by a chemical/physical deposition process. Spacers are deposited conformally on mandrels and then selectively removed, precisely defining final pattern dimensions without mechanical force or deformation, thereby improving reliability while adding a controlled process step
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the margin between vias and source/drain contact layers, reducing deformation issues and ensuring efficient electrical connection, thus enhancing the design flexibility and reliability of semiconductor devices.
Implementation Method 1
adjusting a width of the first photo resist pattern comprises a directional etching process or a directional ion implantation process
Implementation Method 2
the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern
Data Source
AI summary
In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.