Self-Aligned Hard Mask Cut Structure for SADP Overlay Control

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Solution Overview

Problem

Aggressive scaling down of IC dimensions leads to overlay issues during semiconductor fabrication, causing conductive bridges and performance degradation due to challenges in controlling line end distance and selectivity between adjacent materials in self-aligned double patterning (SADP).

Innovation Solution

A self-aligned cut process is introduced using alternately formed first and second hard masks with spacers, providing different etching selectivity to create larger line end windows, mitigating overlay issues and enabling higher pattern density by forming cuts in the hard masks and filling them with conductive material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If IC dimensions are scaled down to increase production efficiency and lower costs, then productivity improves, but manufacturing precision deteriorates due to overlay issues and difficulty in controlling line end distance

Engineering Contradiction:
Improveproduction efficiencyVSAvoidline end distance control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the patterning process into multiple steps using self-aligned double patterning (SADP). First mandrels are formed, then spacers are deposited on their sidewalls to create additional patterns. This segmentation allows each step to be controlled independently, improving line end distance control while maintaining high productivity through systematic scaling

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by forming spacers on mandrel sidewalls before removing the mandrels. This preliminary spacer formation establishes precise pattern positions and line end distances before the actual conductive feature formation, ensuring manufacturing precision is achieved in advance of the critical patterning steps

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If self-aligned double patterning is used to maintain alignment, then manufacturing precision improves, but device complexity increases due to multiple process steps and material selectivity challenges

Engineering Contradiction:
ImprovealignmentVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent introduces spacers as intermediary structures between the mandrels and the final conductive patterns. These spacers serve as mediators that transfer the pattern information while maintaining precise alignment, reducing the direct complexity of the patterning process by breaking it into manageable intermediate steps with clear selectivity requirements

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If pattern density is increased to improve chip performance, then productivity improves, but reliability deteriorates due to conductive bridges and overlay issues

Engineering Contradiction:
Improvepattern densityVSAvoidconductive bridge prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent employs self-aligned processes where spacers automatically form on mandrel sidewalls and subsequent etching steps use these spacers as self-aligned masks. This self-service mechanism ensures that pattern spacing and line end distances are inherently controlled by the spacer thickness rather than requiring precise overlay alignment, preventing conductive bridges while enabling high pattern density

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces manufacturing defects and current leakage, improving semiconductor performance by maintaining alignment and reducing conductive bridges, thereby enhancing the reliability and efficiency of the semiconductor structure.

Implementation Method 1

forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space

Methodology Applied
Scientific EffectEtching selectivity:

Implementation Method 2

depositing a cut hard mask in the first cut and the second cut

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Data Source

PatentUS11848207B2Method and structure of cut end with self-aligned double patterning
Publication Date: 2023.12.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11848207B2 patent drawing
  • US11848207B2 patent drawing
  • US11848207B2 patent drawing

AI summary

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.