Stress-Controlled Hard Mask for Transistor Depth Loading
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Solution Overview
Problem
The existing photolithographic patterning and etching processes for semiconductor waffer fabrication face challenges in achieving uniform etch depth across different trench sizes, leading to non-uniformity and increased depth loading in dielectric structures.
Innovation Solution
The application of mechanical stresses through the composition of the hard mask layer, specifically using compressive or tensile stresses, to control the critical dimension and depth of the CPODE structures, thereby reducing depth loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic patterning and etching processes are used, then the fabrication process is simple and straightforward, but the etch depth uniformity deteriorates across different trench sizes leading to increased depth loading
Solution Approach 1:
The patent applies preliminary action by introducing a stress-controlled hard mask layer before the etching process. The hard mask layer is deposited with specific stress characteristics (tensile or compressive) that pre-compensate for the expected etch depth variations. This preliminary stress application modifies the substrate conditions prior to etching, enabling uniform etch depths across isolated and dense trenches without requiring complex real-time adjustments during the etching process itself.
Solution Approach 2:
The patent utilizes parameter changes by varying the stress state of the hard mask layer to control etch behavior. By adjusting the stress parameter (tensile or compressive) of the hard mask layer, the etch rate and etch depth uniformity are modified. This allows the same etching process to achieve consistent results across different trench geometries by changing the physical state of the mask layer rather than changing the etching process parameters.
2Manufacturing precision
If stress-controlled hard mask layers are applied to improve etch uniformity, then depth loading is reduced to within ±60 nanometers, but the process requires additional layers and steps
Solution Approach 1:
The hard mask layer serves multiple functions simultaneously: it acts as the patterning mask for defining trench geometries, provides stress control to compensate for etch depth variations, and serves as an etch stop layer. By making the hard mask layer multi-functional, the patent eliminates the need for separate stress-control layers or additional process steps, thereby achieving depth loading control without proportionally increasing process complexity.
Solution Approach 2:
The patent changes the physical parameter of the hard mask layer (its stress state) to achieve depth loading control. By depositing the hard mask layer with controlled tensile or compressive stress, the process achieves precise depth control (within ±60 nm) using the same basic deposition and etching equipment, rather than requiring entirely new process equipment or multiple additional process modules.
3Manufacturing precision
If different trench sizes are etched using conventional processes, then the fabrication process is fast and efficient, but the critical dimension uniformity deteriorates between isolated and dense trenches
Solution Approach 1:
The stress-controlled hard mask layer performs preliminary compensation for the loading effects that would otherwise cause critical dimension variations. By pre-establishing the stress state before etching, the process anticipates and corrects for the differences between isolated and dense trench etching, enabling uniform critical dimensions across all trench types without requiring slower, more complex multi-step etching processes.
Solution Approach 2:
The patent changes the stress parameter of the hard mask layer to directly control the etch front behavior. This parameter change enables the etching process to maintain uniform critical dimensions across different trench densities while preserving high throughput, as the stress control is built into the mask layer itself rather than requiring iterative process adjustments during etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the depth loading of dielectric structures to within ±60 nanometers, improving etch uniformity and reducing leakage current, which enables consistent performance of semiconductor devices.
Implementation Method 1
A hard mask layer is formed over the substrate that exerts a compressive force
Data Source
AI summary
Method for reducing the depth loading of dielectric structures on a substrate are disclosed. The substrate includes a set of isolated long dummy gate regions and a set of dense long dummy gate regions. Each dummy gate region is surrounded on each lateral side by a dielectric spacer and a continuous etch stop layer. A hard mask layer is formed over the substrate to exert a force that reduces stresses within the substrate. Each dummy gate is then etched to form an isolation volume and a trench in the substrate, and then filled with dielectric material to form a dielectric structure. The depth loading, or the difference in trench depths between the set of isolated long dielectric structures and the set of dense short dielectric structures, is thus reduced.