Semiconductor Hard Mask Etching Across Integrated Device Regions
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Solution Overview
Problem
The complexity and cost of semiconductor manufacturing processes are increasing due to the complexity of handling different device regions on a chip, necessitating a reduction in process complexity and manufacturing cost.
Innovation Solution
A method involving the use of patterned photoresist layers to selectively remove hard mask and dielectric layers in semiconductor structures, utilizing controlled etching processes to integrate the manufacturing processes of different device regions, thereby reducing the number of process steps and photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate processing is performed for different device regions on a chip, then device performance can be optimized, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the processing of different device regions (first device region with stacked structure and second device region with separate structure) into a single integrated process flow. By forming a unified patterned photoresist layer that simultaneously defines both regions, and performing a single etching process to remove exposed hard mask and dielectric layers, the method combines multiple separate processing steps into one, thereby reducing process complexity while maintaining the ability to optimize different device regions
Solution Approach 2:
The patterned photoresist layer serves multiple functions: it acts as a mask for both the first device region and second device region, defines patterns for different structures (stacked and separate), and enables simultaneous processing of heterogeneous device regions. This multi-functional approach eliminates the need for multiple specialized photomasks and processing steps for different regions
2Manufacturing precision
If multiple photomasks are used for different device regions, then processing precision can be maintained, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple photomask functions into a single patterned photoresist layer. This unified mask simultaneously defines the patterns for both the first device region (with stacked structure including charge storage layer and conductive layers) and the second device region (with separate structure), eliminating the need for multiple sequential photomasking steps and reducing manufacturing cost while maintaining processing precision through proper photoresist formulation and patterning
3Manufacturing precision
If multiple etching steps are performed for different layers, then layer selectivity can be achieved, but process time increases
Solution Approach 1:
The patent merges multiple etching steps into a single etching process by carefully controlling the etching conditions. The etching process selectively removes the hard mask layer and dielectric material layer that are exposed by the patterned photoresist layer, while the photoresist-protected regions remain intact. This single selective etching step achieves the same layer selectivity as multiple separate etching steps would provide, but in one continuous operation, thereby reducing process time
Solution Approach 2:
The patent utilizes parameter changes in the etching process to achieve layer selectivity. By controlling etching parameters (such as etchant composition, temperature, pressure, and power for plasma etching), the process is tuned to selectively etch specific layers (hard mask and dielectric material) at different rates, enabling single-step selective removal of exposed layers while preserving photoresist-protected regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process by integrating device regions, reducing the number of process steps and photomasks, thus lowering the overall complexity and cost.
Implementation Method 1
The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask
Data Source
AI summary
A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.