Hard Mask Deposition for Etch Stop Layer
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Solution Overview
Problem
Current hard mask materials in semiconductor device fabrication face challenges in maintaining critical dimension control during aggressive etching processes, particularly when forming deep trenches with small dimensions, leading to edge etching and inaccurate pattern transfer.
Innovation Solution
A method involving the deposition of an etch-stop layer on a patterned hard mask, where a passivation material is selectively deposited to fill gaps in the hard mask, followed by an etch-stop layer, which enhances etch resistivity and reduces damage to the underlying hard mask, allowing for selective etching and improved pattern fidelity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current hard mask materials are used during aggressive etching processes, then etching can proceed effectively, but edge etching occurs and critical dimension control is lost
Solution Approach 1:
The hard mask structure is segmented into multiple layers with different materials (first hard mask layer, second hard mask layer, capping layer) to distribute the etching resistance function across different components, allowing aggressive etching while maintaining dimensional control
Solution Approach 2:
The patent uses composite hard mask structures combining different materials (e.g., silicon nitride, silicon oxide, tantalum nitride) with complementary properties to achieve both high etch resistance and precise dimensional control during aggressive etching processes
2Ease of manufacture
If hard mask thickness is reduced to lower manufacturing costs, then throughput increases, but pattern transfer fidelity deteriorates
Solution Approach 1:
The patent employs composite hard mask structures where multiple thinner layers work together to provide sufficient pattern transfer fidelity, enabling cost-effective manufacturing without sacrificing precision
Solution Approach 2:
The patent modifies the compositional parameters of the hard mask layers (material composition, layer thickness distribution) to optimize the balance between manufacturing cost and pattern transfer fidelity
3Manufacturing precision
If photoresists and hard masks are used to regulate etching areas, then material removal is controlled, but edge etching occurs during prolonged etching processes
Solution Approach 1:
The patent applies preliminary protective actions by depositing capping layers and using multi-layer hard mask structures before the etching process to pre-establish protection against edge etching during prolonged etching operations
Solution Approach 2:
The hard mask structure includes built-in protective layers that act as a cushion against edge etching, providing beforehand protection that maintains etch area control while preventing harmful edge effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the thickness of the hard mask while maintaining or improving pattern transfer fidelity, potentially reducing manufacturing costs and increasing throughput by minimizing edge erosion and ensuring precise etching.
Implementation Method 1
a deposition assembly, such as, but not limited to, an atomic layer deposition (ALD) assembly, a chemical vapor deposition (CVD) assembly, or a plasma enhanced chemical vapor deposition (PECVD) assembly
Implementation Method 2
plasma enhanced chemical vapor deposition (PECVD) assembly
Data Source
AI summary
The disclosure relates to methods of depositing an etch-stop layer on a patterned hard mask is disclosed. The method comprises providing a substrate comprising the patterned hard mask in a reaction chamber, selectively depositing passivation material on the first material; and selectively depositing an etch-stop layer on the on the second material. The patterned hard mask comprises a first material and a second material, and the second material forms partially the surface of the substrate. The disclosure further relates to a semiconductor structure, to a device and to a deposition assembly.