Replacement Gate Hard-Mask Planarization for Uniform Gate Heights

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Solution Overview

Problem

In semiconductor IC fabrication, particularly at advanced process nodes like 20 nm and 16 nm, maintaining uniform polysilicon gate heights across different areas of a chip is challenging, leading to issues such as gate height loading, dielectric residue, and incomplete poly-cut during the replacement-gate process.

Innovation Solution

A method involving the formation of an etch stop layer and inter-layer dielectric layer, followed by chemical mechanical planarization and selective etching processes, ensures the polysilicon gates are uniformly heighted before replacement, addressing the challenges of non-uniform gate heights and residue issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If polysilicon gates are formed in different areas of an IC, then the gates can accommodate different gate lengths and fabrication steps, but the gate heights become non-uniform

Engineering Contradiction:

Improvedifferent gate lengths and fabrication stepsVSAvoidgate height uniformity

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming an etch stop layer and inter-layer dielectric layer before the replacement gate process, then performing chemical mechanical planarization to pre-establish uniform gate heights. This preparatory planarization ensures that subsequent etching processes can uniformly remove the polysilicon gates across different areas, solving the non-uniformity problem while maintaining adaptability for different gate lengths and fabrication steps.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If replacement gate process is performed without preliminary planarization, then the process is simpler and faster, but dielectric residue and incomplete poly-cut problems occur

Engineering Contradiction:

Improveprocess speedVSAvoidcomplete gate replacement

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent introduces preliminary planarization actions (forming etch stop layer, inter-layer dielectric layer, and chemical mechanical planarization) before the replacement gate process. This ensures uniform gate heights are established in advance, allowing the subsequent replacement process to proceed efficiently without causing dielectric residue or incomplete poly-cut, thus maintaining both productivity and reliability.

Inventive Principle:

Principle #10Preliminary action

3Manufacturing precision

If chemical mechanical planarization is performed to uniform gate heights, then over-etching is reduced, but additional process steps are required

Engineering Contradiction:

Improvegate height uniformityVSAvoidnumber of process steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs chemical mechanical planarization as a preliminary action before the replacement gate process to establish uniform gate heights. This upfront planarization prevents over-etching during the replacement process, improving manufacturing precision. The additional process steps are justified by the significant reduction in defects and improved device uniformity.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in polysilicon gates with near uniform heights, reducing over-etching and residue problems, thereby facilitating smoother subsequent gate replacement processes and improving device uniformity and efficiency.

Implementation Method 1

performing a chemical mechanical planarization (CMP) process to partially remove the dielectric layer

Methodology Applied

Scientific EffectChemical mechanical planarization:

Implementation Method 2

performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS11756838B2Replacement gate process for semiconductor devices

Publication Date: 2023.09.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.