Hard Mask Landing Etch for Via Overlay Error Margin
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Solution Overview
Problem
In semiconductor device fabrication, improved overlay control is challenging during metal etching due to reduced dimensions, leading to increased errors and formation of pits/voids in metal lines and vias, especially with the misalignment of lithography blocking layers.
Innovation Solution
A directional patterning technique is employed to increase the error margin in overlay control by removing portions of the hard mask layer surrounding the via, creating a metal landing margin, which widens the opening and exposes the upper surface of the insulating layer, thereby reducing the occurrence of pits or voids during metal interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional metal etching is performed with lithography blocking layer alignment, then manufacturing process simplicity is maintained, but overlay control precision deteriorates due to reduced dimensions
Solution Approach 1:
The patent applies preliminary action by performing directional patterning on the hard mask layer before the metal etching process. This pre-processing step creates a modified hard mask structure with removed portions that will serve as a compensation mechanism for overlay errors during subsequent etching, thereby improving overlay control in advance of the actual metal patterning
Solution Approach 2:
The patent applies segmentation by dividing the hard mask layer into distinct regions - portions are selectively removed to create separate zones that define the metal landing area. This segmentation creates a more robust structure that is less sensitive to alignment variations, improving overlay control through structural division
2Length of moving object
If metal etching is performed with reduced dimensions, then device scaling is achieved, but overlay control precision deteriorates due to increased sensitivity to misalignment
Solution Approach 1:
The patent applies beforehand cushioning by creating a metal landing margin through directional patterning that removes portions of the hard mask layer. This margin acts as a buffer zone that compensates for potential overlay errors, providing a cushion against misalignment effects that would otherwise be magnified by the reduced dimensions
Solution Approach 2:
The patent applies local quality by creating non-uniform hard mask structures where portions are selectively removed to create areas with different properties. The modified regions provide enhanced tolerance to overlay errors locally, allowing the structure to maintain precision despite overall dimension reduction
3Ease of manufacture
If lithography blocking layer alignment is maintained, then process simplicity is preserved, but pit and void formation increases due to overlay errors
Solution Approach 1:
The patent applies preliminary action by modifying the hard mask layer structure before metal deposition and etching. This pre-modification creates a more forgiving template that reduces the likelihood of pit and void formation during subsequent processing, improving reliability without adding complex alignment steps
Solution Approach 2:
The patent applies the intermediary principle by using the modified hard mask layer as a mediator between the lithography blocking layer and the metal layer. The hard mask with removed portions acts as a buffer that absorbs alignment variations, preventing them from directly causing defects in the metal interconnect structure
Data Source
AI summary
A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.