Hard Mask Offset Spacer Patterning for High-K Metal Gate Integrity
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Solution Overview
Problem
The existing fabrication processes for advanced integrated circuits face challenges in maintaining uniformity and reducing variability in transistor characteristics due to complex process sequences and material modifications, particularly when using high-k dielectric materials and polysilicon-based gate electrode structures, which can lead to increased leakage currents and threshold voltage variability.
Innovation Solution
The proposed solution involves forming gate electrode structures using a dielectric cap material with a hard mask material to enhance etch resistivity, allowing for efficient adaptation of layer thickness and reduced material removal, thereby maintaining gate height uniformity and minimizing metal silicide formation, especially by using sacrificial spacer elements to decouple the dielectric cap layer thickness from the offset spacer element thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex process sequence is used for fabricating high-k metal gate structures, then transistor performance can be improved, but manufacturing precision and uniformity deteriorate due to accumulated process variability
Solution Approach 1:
The fabrication process is divided into distinct segments: forming the dielectric cap layer with controlled thickness, depositing the hard mask material, patterning the offset spacers, and selective removal steps. Each segment is independently optimized to reduce cumulative process variability and maintain gate height uniformity across different transistor regions.
Solution Approach 2:
The dielectric cap layer is formed in advance with a thickness greater than the final required offset spacer thickness. This preliminary structure serves as a sacrificial element that is selectively removed later, allowing precise control of the final gate height without relying on multiple thin deposition steps that would accumulate variability.
2Manufacturing precision
If material removal is performed to adapt layer thickness, then gate height uniformity can be improved, but the risk of creating metal silicide areas increases
Solution Approach 1:
A hard mask material is introduced as an intermediary layer between the dielectric cap and the metal layers. This hard mask material has superior etch resistivity compared to polysilicon, acting as a protective barrier that prevents metal diffusion and silicide formation during etching and thermal processing steps, while still allowing precise thickness adaptation of the dielectric cap layer.
Solution Approach 2:
The etch resistivity parameter of the mask material is changed from polysilicon to a hard mask material with superior etch resistance. This parameter change enables selective removal of the dielectric cap layer without compromising the integrity of the underlying metal structures, thereby preventing unwanted metal silicide formation while maintaining gate height uniformity.
3Ease of manufacture
If polysilicon-based gate electrode structures are used, then manufacturing is simplified, but etch resistivity is insufficient leading to poor definition of offset spacers
Solution Approach 1:
The gate electrode structure is transformed from a simple polysilicon-based structure to a composite structure comprising a dielectric cap layer, a hard mask material layer, and metal gate layers. This composite structure combines the manufacturing simplicity of polysilicon processes with the superior etch resistivity of hard mask materials, enabling precise definition of offset spacers while maintaining ease of manufacture through standardized deposition and patterning techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces transistor variability and failure rates by ensuring uniform removal of placeholder materials and maintaining the integrity of dielectric cap materials, leading to improved transistor characteristics and reduced threshold voltage variability.
Implementation Method 1
a hard mask material having superior etch resistivity compared to resist materials may be provided after patterning the gate electrode structures and forming offset spacer elements
Implementation Method 2
using sacrificial spacer elements to decouple the dielectric cap layer thickness from the offset spacer element thickness
Data Source
AI summary
When forming transistor elements on the basis of sophisticated high-k metal gate structures, the efficiency of a replacement gate approach may be enhanced by more efficiently adjusting the gate height of transistors of different conductivity type when the dielectric cap layers of transistors may have experienced a different process history and may thus require a subsequent adaptation of the final cap layer thickness in one type of the transistors. For this purpose, a hard mask material may be used during a process sequence for forming offset spacer elements in one gate electrode structure while covering another gate electrode structure.