Hard Mask Passivation for Interconnect Etching Precision
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Solution Overview
Problem
The challenge in semiconductor integrated circuit manufacturing lies in the difficulty of shrinking the interconnect structure, particularly due to alignment issues and overlay errors, which lead to defects such as bridging, necking, and leakage currents, as the spacing between features decreases.
Innovation Solution
The technique involves forming a hard mask on inter-level dielectric layers and using a passivation agent during etching to reduce inadvertent etching of the hard mask, thereby increasing the precision of recess formation and reducing the adverse effects of overlay errors, allowing for more precise conductive line and via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the spacing between interconnect features is decreased to increase functional density, then production efficiency increases and costs decrease, but alignment issues and overlay errors increase leading to defects such as bridging, necking, and leakage currents
Solution Approach 1:
A passivation agent is introduced as an intermediary substance during the etching process. This agent selectively passivates the hard mask material, creating a protective layer that prevents etchant from attacking the mask. This intermediary mechanism allows for more tolerant alignment conditions while maintaining precise feature definition, thereby resolving the contradiction between reduced spacing and alignment precision.
Solution Approach 2:
The etching process parameters are modified by introducing a passivation agent that changes the chemical environment. This parameter change allows the etching process to be more selective and less sensitive to alignment variations, enabling tighter spacing without proportionally increasing overlay errors. The passivation agent alters the etching kinetics to favor the dielectric material over the hard mask, even under less than perfect alignment conditions.
2Ease of manufacture
If conventional etching is used without a passivation agent, then the process is simpler and faster, but inadvertent etching of the hard mask occurs reducing precision and increasing defects
Solution Approach 1:
The passivation agent serves as a chemical intermediary that selectively interacts with the hard mask material during etching. By forming a protective complex or layer on the mask surface, it prevents the etchant from directly attacking the mask while allowing controlled etching of the dielectric. This intermediary mechanism maintains process simplicity while dramatically improving recess formation precision and reducing mask damage.
3Productivity
If overlay errors are present, then production can continue without stopping, but defects increase and yield decreases unless the acceptable margin of overlay error is increased
Solution Approach 1:
The passivation agent converts the potentially harmful effect of overlay errors into a beneficial outcome. By providing a protective layer on the hard mask, it allows larger overlay variations to occur without causing the usual defects. The harm of relaxed alignment tolerance is transformed into the benefit of continued production with maintained yield, as the passivation prevents the chain of defects that would normally result from overlay errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the acceptable margin of overlay error, reducing defects and enhancing yield by minimizing leakage currents and improving the reliability of the interconnect structure, even when overlay errors persist.
Implementation Method 1
supplying a passivation agent configured to passivate the hard mask
Data Source
AI summary
Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.