Multi-Layer Hard Mask Patterning for Semiconductor Resolution

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Solution Overview

Problem

Conventional double patterning technologies, such as LELE processes, face challenges in producing fine semiconductor patterns due to feature damage and low yield, limiting the resolution of photolithographic processes as semiconductor devices become smaller and more integrated.

Innovation Solution

A method involving the sequential formation of a target layer and multiple hard mask layers, with specific etching processes and material selections, including anisotropic etching and the use of different materials for each mask layer, to create patterned layers that reduce pattern damage and enhance resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional LELE processes are used for double patterning, then fine patterns can be fabricated beyond photolithographic resolution limits, but features are easily damaged leading to low yield

Engineering Contradiction:
Improvepattern resolutionVSAvoidfeature damage and yield
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent divides the patterning process into multiple sequential steps with separate mask layers (first mask layer, second mask layer, third mask layer) formed at different stages. Each mask layer is processed independently with dedicated etching steps, allowing precise control of each pattern segment while minimizing cumulative damage to features.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent forms protective structures and intermediate layers before final pattern transfer. The organic layer is formed and patterned before the metal layer, creating a protective template that guides subsequent etching while preventing damage to underlying features during the patterning process.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If photolithographic processes are used for fabricating semiconductor features, then manufacturing is straightforward, but resolution is limited and cannot produce fine patterns

Engineering Contradiction:
Improveprocess simplicityVSAvoidpattern resolution
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the single photolithographic step into multiple sequential lithography-etching cycles. Each cycle uses a dedicated mask layer formed by photolithography, allowing the process to maintain the simplicity of standard photolithography tools while achieving resolution far beyond their theoretical limits through cumulative pattern refinement.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If multiple etching steps are performed to create fine patterns, then resolution improves, but pattern damage increases and yield decreases

Engineering Contradiction:
Improvecritical dimensionVSAvoidfeature integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent forms an organic layer as a protective cushion between the metal layer and the pattern transfer process. This organic layer absorbs etching damage and mechanical stress during multiple etching steps, protecting the underlying semiconductor features from damage while still allowing precise pattern transfer through controlled etching of the organic layer itself.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent introduces intermediate mask layers (first mask layer, second mask layer, third mask layer) that act as mediators between the photolithographic process and the final pattern. Each intermediate layer transfers part of the pattern information through controlled etching, reducing the stress and damage that would occur in a single direct pattern transfer step.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method improves pattern transfer efficiency, reduces pattern pitch, and achieves smaller critical dimensions, addressing the limitations of conventional double patterning technologies by preventing feature damage and enhancing yield.

Implementation Method 1

etching the patterned upper hard mask layer, the patterned organic layer, the middle hard mask layer, the lower hard mask layer, and a portion of the target layer

Methodology Applied
Scientific EffectAnisotropic etching:

Data Source

PatentUS10153161B1Method for manufacturing a semiconductor structure
Publication Date: 2018.12.11 NAN YA TECH
  • US10153161B1 patent drawing
  • US10153161B1 patent drawing
  • US10153161B1 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes forming a target layer, a lower hard mask layer, a middle hard mask layer, and an upper hard mask layer in sequence on a substrate. A first mask layer is then formed on the upper hard mask layer, wherein the first mask layer has a plurality of openings exposing a portion of the upper hard mask layer. A patterned upper hard mask layer having a plurality of apertures exposing a portion of the middle hard mask layer is formed by etching the exposed portion of the upper hard mask layer. A patterned organic layer is then formed on the exposed portion of the middle hard mask layer. A patterned target layer is formed by etching the patterned upper hard mask layer, the patterned organic layer, the middle hard mask layer, the lower hard mask layer, and a portion of the target layer.