Hard Mask Structure for Semiconductor Device Bridging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down, challenges arise in fabrication due to increased risks of bridging or electrical shorting, which can degrade device performance or cause failures, and existing methods are not entirely satisfactory in addressing these issues.
Innovation Solution
The manufacturing process involves forming a three-dimensional structure with height differences, specifically a FinFET semiconductor device, using techniques such as CMOS technology, where a gate structure is disposed over a fin structure with a spacer and a conductive layer, and a hard mask structure is formed to reduce capacitance and enhance electrical performance by creating air gaps and using materials with different k constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device geometry is scaled down to increase functional density, then the number of interconnected devices per chip area increases, but the risk of bridging or electrical shorting increases
Solution Approach 1:
The fabrication process is divided into multiple sequential steps including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows precise control over feature formation and spacing, reducing bridging risks while enabling continued scaling for higher functional density
Solution Approach 2:
Mandrels are formed as preliminary structures that define the positions of subsequent spacer features. The mandrels are removed after serving their guiding purpose, leaving precisely positioned spacer structures. This preliminary action enables accurate feature placement at scaled dimensions without direct patterning, reducing shorting risks
2Ease of manufacture
If existing fabrication methods are used for scaled devices, then manufacturing simplicity is maintained, but bridging or electrical shorting problems occur
Solution Approach 1:
Spacer structures serve as intermediary elements that are formed through deposition and selective removal processes. These spacers act as self-aligned features that define critical dimensions without requiring direct lithographic patterning at the final scale, maintaining manufacturing simplicity while ensuring reliable feature separation
Solution Approach 2:
The fabrication process utilizes changes in material properties and deposition parameters to form spacers with specific thicknesses and compositions. By controlling deposition conditions and selective removal parameters, the process achieves precise feature definition at scaled dimensions while using standard fabrication techniques
Data Source
AI summary
A semiconductor device includes a gate electrode, spacers and a hard mask structure. The spacers are disposed on opposite sidewalls of the gate electrode. The hard mask structure includes a first hard mask layer and a second hard mask layer. A lower portion of the first hard mask layer is disposed between the spacers and on the gate electrode, and a top portion of the first hard mask layer is surrounded by the second hard mask layer.